Skip to content
STIMSMITH

co-simulation methodology

Concept WIKI v1 · 5/28/2026

In the provided RISC-V verification evidence, co-simulation methodology is a dynamic verification approach that runs an RTL CPU core alongside an instruction-set simulator reference model, such as Spike, and cross-checks instruction execution, memory transactions, and trace logs to detect mismatches.

Overview

In the RISC-V CPU verification context shown by the Ibex testbench, co-simulation methodology refers to running a design under test, such as an RTL CPU core, together with a reference instruction-set simulator (ISS) and comparing their behavior. The Ibex UVM testbench uses this methodology to cross-check Ibex execution against the Spike ISS reference model. [C1]

How it is used in Ibex verification

The Ibex testbench stimulates the core to execute a program stored in memory. During execution, the core's trace log is compared with a golden-model ISS trace log from Spike; this cross-check is used to ensure correctness of execution. The testbench also collects coverage information about executed instructions and operands, with a test plan and coverage plan used to guide verification coverage. [C2]

A provided co-simulation system can run either in the Ibex UVM DV environment or with Simple System. In this system, a RISC-V ISS is run in lockstep with the Ibex core. All instructions executed by Ibex and memory transactions generated by Ibex are checked against the behavior of the ISS. [C3]

Synchronization and external events

The co-simulation system supports memory errors, interrupt requests, and debug requests. These events are observed in the RTL simulation and forwarded to the ISS so that the ISS and RTL model remain synchronized. [C4]

The RISC-V Formal Interface (RVFI) is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [C5]

Tool and implementation notes

In the evidence, Spike is the currently supported ISS for the Ibex co-simulation system, and running the co-simulation system requires a particular version of Spike. The system is described as using a generic interface intended to allow support for multiple ISSes, although only Spike is currently supported. [C6]

The evidence also notes that only VCS is supported as a simulator for this co-simulation system, while adding support for another simulator should be straightforward because no VCS-specific functionality is required. [C7]

Role in verification closure

Within the Ibex verification flow, co-simulation is combined with randomized and directed testbench stimulus. The Ibex UVM environment runs binaries built from source produced by the RISC-DV random instruction generator, and the testbench can add randomized memory timings, memory errors, interrupts, and debug requests. A comprehensive test plan and coverage plan are implemented around this flow. [C8]

LINKED ENTITIES

4 links
UVM Based Design Verification of a RISC-V CPU Core USES
Ibex Core USES
spike USES
RISC-V Formal Interface (RVFI) USES

CITATIONS

8 sources
8 citations
[1] Ibex uses a UVM-based testbench employing co-simulation to cross-check execution against the Spike ISS reference model. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The Ibex testbench executes programs from memory, compares the core trace log against a Spike golden-model trace log, and collects coverage for executed instructions and operands. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] The Ibex co-simulation system can run in the Ibex UVM DV environment or with Simple System, running a RISC-V ISS in lockstep with Ibex and checking executed instructions and memory transactions against the ISS. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The co-simulation system supports memory errors, interrupt requests, and debug requests by observing them in RTL simulation and forwarding them to the ISS to keep the RTL and ISS in sync. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] The co-simulation system currently supports only Spike as its ISS and requires a particular version of Spike, while using a generic interface intended to support multiple ISSes. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[7] Only VCS is supported as a simulator for the co-simulation system, although no VCS-specific functionality is required and adding another simulator should be straightforward. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[8] The Ibex verification flow runs binaries built from RISC-DV-generated source and adds randomized memory timings, memory errors, interrupts, and debug requests, with a comprehensive test plan and coverage plan. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi