Ibex Core
ToolIbex Core is an open-source 32-bit RISC-V CPU core written in SystemVerilog and maintained by lowRISC. It is highly parameterizable for embedded-control use cases and is verified with a UVM-based testbench using co-simulation against Spike, memory and interrupt agents, a memory model, and RVFI-based checking.
First seen 5/27/2026
Last seen 5/28/2026
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Overview
Ibex Core is an open-source 32-bit RISC-V CPU core written in SystemVerilog and maintained by lowRISC. The provided thesis evidence describes it as production-quality, heavily parameterizable, suited for embedded control applications, and having undergone extensive verification and multiple tape-outs. The public lowRISC GitHub repository describes Ibex as a small 32-bit RISC-V CPU core, previously known as zero-riscy.
Ibex supports the RISC-V Integer (I) or Embedded (E) base, Integer Multiplication and Division (M), Compressed (C), and Bit Manipulation (B) extensions. The evidence also identifies Ibex as being used in OpenTitan, an open-source silicon Root of Trust project.
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9 connectionsIbex Core is verified using a UVM-based testbench.
The paper discusses the Ibex Core as a state-of-the-art RISC-V CPU verification example.
Ibex Core verification uses Spike as a golden ISS reference model for co-simulation.
Ibex verification employs a co-simulation methodology.
Ibex testbench instantiates memory interface agents for instruction and data memory accesses.
Ibex testbench uses an interrupt agent to drive stimulus on interrupt pins.
Ibex testbench instantiates a memory model for instruction and data memory.
Ibex Core uses the RISC-V Formal Interface for co-simulation checking.
Ibex Core is a RISC-V CPU core implementing the RISC-V ISA.
LINKED ENTITIES
9 linksUVM Based Design Verification of a RISC-V CPU Core MENTIONS Extracted graph relationship
RISC-V IMPLEMENTS Extracted graph relationship
UVM USES Extracted graph relationship
spike USES Extracted graph relationship
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Interrupt Agent USES Extracted graph relationship
Memory Model USES Extracted graph relationship
RISC-V Formal Interface USES Extracted graph relationship
CITATIONS
15 sources15 citations — click to expand
[1] Ibex is an open-source 32-bit RISC-V CPU core written in SystemVerilog and maintained by lowRISC. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[2] The public lowRISC GitHub repository describes Ibex as a small 32-bit RISC-V CPU core, previously known as zero-riscy. lowRISC/ibex
[3] Ibex is heavily parameterizable, suited for embedded control applications, has undergone extensive verification, and has seen multiple tape-outs. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[4] Ibex supports the RISC-V I or E, M, C, and B extensions. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[5] Ibex is used in OpenTitan, described in the evidence as an open-source silicon Root of Trust project. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[6] Ibex is verified using a UVM-based testbench with co-simulation against Spike, and the testbench runs binaries generated from RISC-DV source. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[7] The Ibex testbench stimulates the core to execute a program from memory, compares the core trace log to a Spike trace log, and collects instruction and operand coverage. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[8] The Ibex testbench adds randomized memory timings, memory errors, interrupts, and debug requests as stimulus. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[9] Two memory interface agents are used in the Ibex testbench, one for instruction fetch and one for the LSU interface. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[10] The interrupt agent drives randomized stimulus onto Ibex interrupt pins during test execution. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[11] The Ibex testbench uses a single memory model loaded with the compiled assembly test program and serving requests from both memory interface agents. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[12] Ibex tests extend core-ibex-base-test and coordinate binary loading, core-status checking, timeouts, and interrupt/debug stimulus. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[13] The Ibex co-simulation system runs a RISC-V ISS in lockstep with Ibex, currently supports Spike, checks instructions and memory transactions against the ISS, and forwards observed RTL memory errors, interrupt requests, and debug requests to keep the ISS synchronized. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[14] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[15] Because Ibex has many parameters, verification closure targets supported configurations rather than all possible parameter sets; the cited evidence focuses on the OpenTitan configuration and reports 90% code and functional coverage with over 90% regression pass rate. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi