Instruction Set Compliance Testing

Concept

Instruction set compliance testing is a processor-verification activity used to check whether a CPU core correctly implements its target instruction set. In the provided evidence, it appears in a UVM-based RISC-V verification flow that integrates the RISC-V compliance test suite and uses Spike, a RISC-V instruction set simulator, to validate correct instruction execution.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Instruction set compliance testing is a verification activity focused on checking that a processor core behaves correctly with respect to its instruction set architecture. In the available evidence, the concept is discussed in the context of verifying a RISC-V CPU core, where ensuring the correctness and reliability of RISC-V cores is described as requiring a robust and effective verification process.

Role in a RISC-V verification flow

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← uses 95% 2e

The paper uses the RISC-V compliance test suite for instruction set compliance testing.

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] The UVM-based RISC-V CPU verification work includes an instruction set compliance test as part of its experimental evaluation. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The verification infrastructure integrates open-source tools from the RISC-V toolchain and the RISC-V compliance test suite available from the RISC-V organization. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The infrastructure incorporates Spike, a RISC-V instruction set simulator, to validate correct instruction execution. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] The broader RISC-V verification infrastructure also uses UVM, SystemVerilog, direct tests, benchmarks, a random instruction generator, and coverage-driven verification concepts. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi