Renato Occhineri

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Renato Occhineri is the author of the 2023–24 master's thesis "UVM based design verification of a RISC-V CPU core" in Electronics Engineering. The thesis presents a UVM/SystemVerilog verification infrastructure for a RISC-V CPU core, using RISC-V open-source tooling, compliance tests, random and directed testing, benchmarks, and Spike for instruction-execution validation.

First seen 5/27/2026

Last seen 5/28/2026

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Renato Occhineri is listed as the author of "UVM based design verification of a RISC-V CPU core", a Tesi di Laurea Magistrale in Electronics Engineering - Ingegneria Elettronica. The thesis identifies Prof. Franco Zappa as advisor and the 2023–24 academic year as its academic year. [C1]

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UVM Based Design Verification of a RISC-V CPU Core ← authored by 100% 1e

The thesis paper is authored by Renato Occhineri.

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[1] Renato Occhineri authored the thesis "UVM based design verification of a RISC-V CPU core," a Tesi di Laurea Magistrale in Electronics Engineering - Ingegneria Elettronica, advised by Prof. Franco Zappa in academic year 2023–24. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The thesis frames RISC-V as flexible, scalable, and customizable, and connects its importance to open-source hardware platforms for IoT and edge computing. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] The thesis presents a UVM-based verification infrastructure for a RISC-V core and emphasizes UVM and SystemVerilog for efficient and reliable verification. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] The verification infrastructure integrates RISC-V toolchain tools, the RISC-V compliance test suite, a random instruction generator, direct tests, benchmarks, and Spike. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] The thesis states that the infrastructure supports coverage-driven verification, reusable components, and high-performance simulation while demonstrating the benefits of standardized methodologies, open-source ecosystems, and thorough testing for RISC-V verification. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi