Overview

Renato Occhineri is listed as the author of "UVM based design verification of a RISC-V CPU core", a Tesi di Laurea Magistrale in Electronics Engineering - Ingegneria Elettronica. The thesis identifies Prof. Franco Zappa as advisor and the 2023–24 academic year as its academic year. [C1]

Thesis focus

Occhineri's thesis addresses verification of RISC-V CPU cores. It frames RISC-V as an instruction-set architecture valued for flexibility, scalability, and customizability, particularly in relation to open-source hardware platforms for IoT and edge-computing applications. The work argues that correctness and reliability of RISC-V cores require a robust verification process. [C2]

Verification infrastructure

The thesis presents a UVM-based verification infrastructure for a RISC-V core, emphasizing the use of UVM and SystemVerilog to support efficient and reliable verification. [C3]

The proposed infrastructure includes:

• open-source tools from the RISC-V toolchain;
• the RISC-V compliance test suite;
• a random instruction generator;
• specifically designed direct tests;
• benchmarks tailored to the RISC-V core; and
• Spike, a RISC-V instruction-set simulator used to validate correct instruction execution. [C4]

According to the thesis abstract, these components support coverage-driven verification, reusable components, and high-performance simulation, while the overall methodology demonstrates the benefits of standardized verification methods, open-source software ecosystems, and broad testing strategies for RISC-V core verification. [C5]

Related work

• [[UVM Based Design Verification of a RISC-V CPU Core]]