Overview
ImperasDV is described as a tool that integrates fast reference models for RISC-V into verification flows. Its primary role in the provided evidence is to enable lock-step comparison of RTL against a golden reference model at instruction retirement, helping detect mismatches early in processor verification. [ImperasDV reference-model integration] [ImperasDV lock-step comparison]
Role in RISC-V verification
In the cited RISC-V verification flow, ImperasDV is used as part of a broader toolbox that combines simulation, directed and constrained-random tests, debug, and coverage analysis. The evidence states that ImperasDV enables lock-step comparison against a reference model, catching errors at instruction retirement. [ImperasDV lock-step comparison]
Lock-step compare is defined as running RTL and a golden reference model in parallel and comparing results at instruction retirement for early bug detection. [Lock-step compare definition]
Included directed test suites
The evidence states that ImperasTS-ISA architectural validation tests, similar to compliance suites, are included with ImperasDV licences. [ImperasTS-ISA inclusion]
The broader ImperasTS family is described as including:
- ImperasTS-ISA for architectural validation tests.
- ImperasTS-VECT for vector extensions.
- ImperasTS-MMU / PMP / ePMP for virtual memory and protection features. [ImperasTS family]
The evidence also states that ImperasTS suites self-check and automatically compare results against a reference model, supporting the discovery of subtle design issues and accelerating coverage closure. [ImperasTS self-checking suites]
Integration with simulation and debug flows
The evidence describes a verification flow in which constrained-random programs can be executed in simulators such as VCS, while Verdi provides centralized debug. In that context, ImperasDV provides lock-step comparison against a reference model. [ImperasDV in VCS-centered flow]
Another evidence passage describes a RISC-V verification flow with ImperasFC functional coverage and an ImperasDV reference model integrated with Verdi for unified coverage analysis in VCS. [ImperasDV VCS and Verdi integration]
Debug and coverage-closure benefits
The evidence states that combining architecturally self-checking tests with lock-step compare in ImperasDV helps engineers identify mismatches immediately, simplifying root-cause analysis. [ImperasDV debug efficiency]
In the same hybrid methodology, directed ImperasTS suites are used after random stimulus to target coverage gaps and support coverage closure. [Hybrid coverage closure]