Lockstep Co-Simulation Methodology
TechniqueFirst seen 7/10/2026
Last seen 7/10/2026
Evidence 3 chunks
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28 connectionsA UVM component feeds results to scoreboards as part of the lockstep co-simulation integration.
The lockstep methodology feeds results to coverage collectors as part of the UVM integration.
A UVM component synchronizes RTL and reference model at retirement and integrates the lockstep flow.
A configurable state mask is used in the lockstep methodology to control which architectural state elements are compared.
RVVI is used as the interface to standardize exchange of retire, state, and event information between DUT, testbench, and reference model in the lockstep methodology.
ImperasDV provides the reference model and lockstep co-simulation methodology integrating with SV/UVM flows and RVVI.
The lockstep co-simulation methodology uses retirement-level step-and-compare to synchronize and compare RTL and reference model states at each retire event.
Checkpoints and consistent seed logging ensure repeatability for long regressions in the lockstep flow.
This paper is cited as a reference for lockstep co-simulation methodology with asynchronous events and stimulus.
This paper is cited as a reference for retirement-level lockstep co-simulation methodology and mismatch reporting.
The lockstep co-simulation methodology runs the RTL alongside a reference model and synchronizes at instruction retirement.
A comprehensive testbench stimulus combines constrained-random instruction streams to expose real bugs in the lockstep methodology.
Directed ISA tests are combined with constrained-random streams as stimulus in the lockstep methodology.
Asynchronous events are injected at random retire points to stress the design in the lockstep methodology.
The lockstep methodology stresses virtual memory operations to trigger corner-case bugs.
The lockstep methodology explores CSR side effects to trigger corner-case bugs.
The lockstep methodology tests weak versus strong memory models to trigger corner-case bugs.
The lockstep co-simulation methodology is implemented using SystemVerilog-based co-simulation flows.
The lockstep co-simulation methodology is applied to verify RISC-V processor designs.
Synopsys documents the lockstep co-simulation methodology for ImperasDV with retirement-level compare and integration with VCS and Verdi.
The lockstep co-simulation methodology implements the lockstep co-simulation concept by running RTL alongside a reference model and comparing architectural state at each instruction retirement.
The lockstep methodology addresses multi-hart RISC-V designs as part of its verification scope.
The methodology synchronizes RTL and reference model at instruction retirement points.
Architectural state is captured and compared at each retire event in the lockstep methodology.
The RTL and reference model run the same programme under a co-simulation harness in the lockstep methodology.
A validated reference model runs alongside the RTL in the lockstep co-simulation methodology.
Non-deterministic sources are masked or stubbed to avoid spurious mismatches in the lockstep methodology.
Seed-based deterministic replay ensures that randomized injections remain reproducible for debugging in the lockstep methodology.