Configurable State Mask

Concept

In RISC-V retirement-level lockstep co-simulation, a configurable state mask selects which subset of architectural state elements are compared at each instruction retirement, allowing verification to scale from fast bring-up checks (e.g., PC only) to comprehensive sign-off coverage of PC, GPRs, CSRs, and memory.

First seen 7/10/2026

Last seen 7/10/2026

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Configurable State Mask

Definition

A configurable state mask is the mechanism inside a retirement-level lockstep co-simulation harness that selects which elements of the architectural state are compared between the RTL design under test (DUT) and the reference model at each instruction retirement. Rather than always comparing the full state, the mask lets verification engineers enable or disable individual categories — program counter (PC), general-purpose registers (GPRs), control and status registers (CSRs), memory, and so on — so that checks match the verification phase and the DUT's maturity.

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Lockstep Co-Simulation Methodology ← uses 93% 2e

A configurable state mask is used in the lockstep methodology to control which architectural state elements are compared.

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Lockstep Co-Simulation Methodology USES Extracted graph relationship

CITATIONS

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[1] The tool provides a configurable state mask, allowing for a structured approach to checking. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[2] Bring-up often starts with PC-only checks, then expands to PC plus GPRs, then CSRs, and finally selected memory regions or complete architectural state for sign-off. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[3] This scalability makes lockstep applicable from early RTL to final verification sign-off. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[4] Configurable architectural state is compared at each retire, with immediate mismatch reporting for faster debug. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[5] Teams often begin with PC plus GPRs for speed, then widen to CSRs and memory as confidence targets grow. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[6] Non-deterministic sources such as timers or random I/O are masked or stubbed to avoid spurious mismatches. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[7] RVVI standardises the exchange of retire, state, and event information between DUT, testbench, and reference model. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

[8] Lockstep comparison flags the first divergent instruction rather than surfacing problems at the end of a test run, enabling point-of-failure debug. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium