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Configurable State Mask

Concept WIKI v1 · 7/10/2026

In RISC-V retirement-level lockstep co-simulation, a configurable state mask selects which subset of architectural state elements are compared at each instruction retirement, allowing verification to scale from fast bring-up checks (e.g., PC only) to comprehensive sign-off coverage of PC, GPRs, CSRs, and memory.

Configurable State Mask

Definition

A configurable state mask is the mechanism inside a retirement-level lockstep co-simulation harness that selects which elements of the architectural state are compared between the RTL design under test (DUT) and the reference model at each instruction retirement. Rather than always comparing the full state, the mask lets verification engineers enable or disable individual categories — program counter (PC), general-purpose registers (GPRs), control and status registers (CSRs), memory, and so on — so that checks match the verification phase and the DUT's maturity.

In the article's terminology, the tool "provides a configurable state mask, allowing for a structured approach to checking" [1]. Conceptually, it is the knob that turns the retirement-level compare step into a phased, scalable verification primitive.

Why it matters

RISC-V designs vary widely: single- or multi-hart, cached or uncached, weak or strong memory model. A single fixed comparison configuration cannot serve every stage of verification efficiently. The configurable state mask is what makes retirement-level lockstep co-simulation "applicable from early RTL to final verification sign-off" [1]:

  • It lets teams tune the compare workload to simulation throughput.
  • It isolates specific subsystems (e.g., CSR privilege logic) by widening only the relevant mask bits.
  • It avoids false positives during bring-up where, for example, memory state is not yet fully modelled.

Typical widening progression

The evidence describes a standard progression used by teams adopting the methodology [1]:

  1. PC only — fastest possible check; useful for control-flow bring-up and early sanity.
  2. PC + GPRs — exercises the datapath and write-back logic for typical instructions.
  3. Add CSRs — validates privilege, exception, and interrupt handling paths.
  4. Selected memory regions or full architectural state — final sign-off confidence, where any divergence is treated as a real bug.

This progression mirrors how confidence targets grow during a project and is a direct application of the configurable state mask.

Role in the lockstep co-simulation methodology

The configurable state mask is one component of the broader Lockstep Co-Simulation Methodology. Its behaviour in context:

  • At each retire event, the RTL and reference model architectural states are captured [1].
  • Only the fields enabled by the mask participate in the equality check; disabled fields are ignored.
  • A divergence on any enabled field is flagged immediately with the retire index and expected-vs-actual values, enabling point-of-failure debug rather than end-of-test diffs [069a0c6f-fd04-4c1a-9744-95377472484d, 8ce294ef-fe54-466a-bf72-8f5b9594b645].
  • Because the compare runs at retirement rather than on transient pipeline state, the mask targets architecturally visible behaviour and avoids spurious mismatches [1].

Practical interactions

  • Non-deterministic sources. Timers or random I/O can produce legitimate RTL-vs-reference differences that are not design bugs. In practice, such sources are masked or stubbed rather than widening the compare mask to "everything" [2].
  • Asynchronous events. Randomised interrupts, exceptions, and debug requests are typically injected via the RVVI-based handshake, while the mask keeps comparison deterministic for replay [2].
  • Bring-up speed. Starting with a narrow mask (e.g., PC only) keeps early regressions short; widening the mask is a deliberate signal that the DUT is ready for deeper checks [069a0c6f-fd04-4c1a-9744-95377472484d, 8ce294ef-fe54-466a-bf72-8f5b9594b645].

Key terms (as used in this context)

  • Architectural State — the processor state visible at the ISA level, including PC, GPRs, CSRs, and relevant memory contents [2].
  • Instruction Retirement — the point at which an instruction has completed execution and its results are committed to the architectural state [2].
  • RVVI (RISC-V Verification Interface) — the open interface used to standardise retire, state, and event exchange between DUT, testbench, and reference model [069a0c6f-fd04-4c1a-9744-95377472484d, 8ce294ef-fe54-466a-bf72-8f5b9594b645].

Takeaway

The configurable state mask is what makes retirement-level lockstep co-simulation practical across the verification lifecycle. By letting engineers choose what to compare at each retire, it converts a single compare primitive into a scalable strategy — fast PC-only checks at bring-up, widening through GPRs and CSRs as the DUT matures, and full architectural-state comparison for sign-off.

CITATIONS

8 sources
8 citations
[1] The tool provides a configurable state mask, allowing for a structured approach to checking. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[2] Bring-up often starts with PC-only checks, then expands to PC plus GPRs, then CSRs, and finally selected memory regions or complete architectural state for sign-off. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[3] This scalability makes lockstep applicable from early RTL to final verification sign-off. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[4] Configurable architectural state is compared at each retire, with immediate mismatch reporting for faster debug. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[5] Teams often begin with PC plus GPRs for speed, then widen to CSRs and memory as confidence targets grow. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[6] Non-deterministic sources such as timers or random I/O are masked or stubbed to avoid spurious mismatches. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[7] RVVI standardises the exchange of retire, state, and event information between DUT, testbench, and reference model. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium
[8] Lockstep comparison flags the first divergent instruction rather than surfacing problems at the end of a test run, enabling point-of-failure debug. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium