Asynchronous Events
ConceptIn the context of RISC-V lockstep co-simulation, asynchronous events are interrupts, debug requests, or exceptions that are injected at arbitrary instruction-retire points to stress a design under test while keeping runs reproducible for debug.
First seen 7/10/2026
Last seen 7/10/2026
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Definition
In RISC-V lockstep co-simulation flows, asynchronous events are stimuli such as interrupts, debug requests, and exceptions that are injected into the design at arbitrary instruction-retire points. Their purpose is to stress the design under test (DUT) while keeping the resulting simulation runs reproducible for debug.
Role in Lockstep Co-Simulation
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1 connectionsAsynchronous events are injected at random retire points to stress the design in the lockstep methodology.
LINKED ENTITIES
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[1] Asynchronous events are interrupts, debug requests, or exceptions injected at arbitrary retire points to stress the design while keeping runs reproducible for debug. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
[2] RVVI ensures that asynchronous events such as interruptions, exceptions, and debug transitions can be introduced and remain reproducible for analysis. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
[3] RVVI extensions ensure randomised injections of asynchronous events remain reproducible for debugging, and a comprehensive testbench combines constrained-random instruction streams with directed ISA tests enhanced with asynchronous events injected at random retire points. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug
[4] An RVVI-based handshake enables randomised interrupts and debug requests while keeping runs deterministic for replay. RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug