Definition
In RISC-V lockstep co-simulation flows, asynchronous events are stimuli such as interrupts, debug requests, and exceptions that are injected into the design at arbitrary instruction-retire points. Their purpose is to stress the design under test (DUT) while keeping the resulting simulation runs reproducible for debug.
Role in Lockstep Co-Simulation
Lockstep co-simulation runs an RTL design in parallel with a validated reference model, synchronising the two at each instruction retirement and comparing architectural state. Asynchronous events are a key ingredient of the stimulus used in this methodology because they force the DUT and the reference model to handle out-of-band control-flow changes (interrupts, exceptions, debug transitions) rather than just steady-state instruction execution. The Alpinum Consulting write-up on retirement-level step-and-compare defines asynchronous events as "Interrupts, debug requests, or exceptions are injected at arbitrary retire points to stress the design while keeping runs reproducible for debug" [chunk 8e94a56d].
RVVI-Mediated Reproducibility
Because asynchronous events are non-deterministic by nature, reproducing them across reruns is essential for root-cause analysis. In modern lockstep flows, this reproducibility is provided through RVVI (the RISC-V Verification Interface), an open standard interface for exchanging retire, state, and event information between the RTL, testbench, and reference models [chunk 8e94a56d]. RVVI extensions ensure that randomised injections of asynchronous events "remain reproducible for debugging" [chunk 069a0c6f]. The same article notes that RVVI also "ensures that asynchronous events such as interruptions, exceptions, and debug transitions can be introduced and remain reproducible for analysis" [chunk 8ce294ef].
Composition of Stimulus
A comprehensive testbench in a lockstep flow typically combines constrained-random instruction streams with directed ISA tests, enhanced with asynchronous events injected at random retire points [chunk 069a0c6f]. Non-deterministic sources such as timers or random I/O are masked or stubbed to avoid spurious mismatches, while an RVVI-based handshake enables randomised interrupts and debug requests while keeping runs deterministic for replay [chunk 069a0c6f].
Types of Asynchronous Events
The evidence identifies the following categories of asynchronous events used in RISC-V lockstep co-simulation:
- Interrupts — asynchronous requests that divert the hart from its current execution flow, used to exercise trap entry, save/restore, and return paths.
- Debug requests — external debug-trigger events that force entry into debug mode, stressing debug-mode entry/exit and debug-state handling.
- Exceptions — synchronous or asynchronous traps (e.g., from CSRs, memory, or privilege transitions) that test exception handling logic.
All three classes are explicitly grouped under asynchronous events in the Appendix A definitions of the Alpinum article [chunk 8e94a56d] and are cited together as the rationale for RVVI-mediated reproducibility [chunk 8ce294ef].
Connection to Step-and-Compare
Step-and-compare is the lockstep methodology in which RTL and reference-model states are captured and compared at each retire step, providing immediate mismatch reporting. Asynchronous events are injected as part of the stimulus feeding this step-and-compare loop; when a mismatch occurs, the flow records the retire index, instruction context, expected versus actual values, and a short preceding window so that engineers can isolate the asynchronous-event interaction that triggered the divergence [chunk 8e94a56d, chunk 069a0c6f].
Related Concept
Asynchronous events are a stimulus component used by the Lockstep Co-Simulation Methodology, where they serve as one of the key sources of stress alongside constrained-random instruction streams and directed ISA tests [chunk 069a0c6f].