Siemens EDA

Organization

Siemens EDA is the electronic design automation division referenced in industry contexts as a provider of verification technologies for RISC-V processor design, including hardware-assisted verification (virtual prototypes, emulation, and hardware prototyping) and SystemVerilog simulation environments used in standards-based RISC-V verification flows such as RVVI and ImperasDV integration.

First seen 6/10/2026

Last seen 9/9/2026

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Siemens EDA

Overview

Siemens EDA is identified in industry sources as an electronic design automation organization that supplies verification technologies used in advanced processor and SoC design flows, including flows targeting the RISC-V instruction set architecture.

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

Andy Meier ← part of 99% 1e

Andy Meier is principal product marketing manager for Siemens EDA.

Emulation uses → 91% 1e

Siemens EDA provides emulation capabilities for RISC-V verification flows.

Virtual Prototype Verification uses → 91% 1e

Siemens EDA provides virtual prototype capabilities for RISC-V verification flows.

ImperasDV uses → 93% 1e

ImperasDV is integrated with Siemens EDA SystemVerilog environments.

Questa ← published by 95% 1e

Questa is a simulator from Siemens EDA.

DVCon Japan 2026 mentions → 97% 1e

Siemens EDA is announced as a participant at DVCon Japan 2026 in Yokohama Kanagawa.

LINKED ENTITIES

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DVCon Japan 2026 MENTIONS Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] Siemens EDA is listed as a participant at DVCon Japan 2026 on September 10, 2026 in Yokohama, Kanagawa. DVCon Japan 2026 listing

[2] Imperas provides examples of use of RVVI with its ImperasDV product with SystemVerilog for use with environments from Cadence, Synopsys, and Siemens EDA. riscv-verification/RVVI

[3] ImperasDV provides integrated solutions for RISC-V processor verification combined with design flow integration for the leading EDA SystemVerilog environments with Cadence, Siemens EDA, and Synopsys. Survey of Verification of RISC-V Processors

[4] Andy Meier, principal product marketing manager for Siemens EDA, stated that hardware-assisted verification such as virtual prototype capabilities, emulation, and hardware prototyping are critical components in the overall RISC-V verification flow. RISC-V Micro-Architectural Verification