Overview
The supplied evidence presents Synopsys primarily in an electronic design automation and semiconductor design-verification context. Synopsys is associated with verification-language and methodology work, including the OpenVera functionality contributed into SystemVerilog and the Synopsys-created Verification Methodology Manual (VMM). [C1][C2]
The evidence also describes Synopsys-related verification tooling and flows, including use of the Synopsys VCS constraint solver for constrained-random microcode stimulus generation and a RISC-V verification methodology involving STING, ImperasTS, ImperasDV, VCS, Verdi, ZeBu, and HAPS. [C3][C4]
Verification language and methodology contributions
A RISC-V verification thesis summarizes the evolution of SystemVerilog from earlier verification languages. It states that SystemVerilog was intended to build on synthesizable Verilog while adding verification features and preserving compatibility with earlier Verilog standards. In that account, the core verification functionality of SystemVerilog was predominantly supported by OpenVera, which was contributed by Synopsys. The same source states that SystemVerilog became IEEE Standard 1800-2005 and was later combined with Verilog IEEE 1364-2005 into IEEE Standard 1800-2009. [C1]
The evidence identifies the Verification Methodology Manual (VMM) as a Synopsys-created methodology. VMM is described as a set of practices for creating reusable verification environments in SystemVerilog, using language features such as object-oriented programming, randomization, constraints, and functional coverage. [C2]
VMM also appears in the evidence as a contributor to the Universal Verification Methodology (UVM) standardization effort. The cited thesis states that the Accellera UVM standard was built through cooperation between EDA vendors and customers, with contributions from the OVM code base and VMM. It also describes UVM as a hybrid of technologies that included Synopsys's VMM-RAL among its origins. [C2]
Constrained-random processor verification
An EE Times article on constrained-random verification describes processor verification as difficult because of factors such as complex instruction sets, pipeline stages, execution strategies, instruction parallelism, scalar and vector operations, and many corner cases. It argues that traditional directed tests had become unreasonable to create at the required scale. The article proposes an object-oriented SystemVerilog approach using top-down stimulus planning and commercially available base classes, including those in Synopsys's VMM. [C5]
The same article states that simple random stimulus is not sufficient for full processor verification because purely random instructions rarely target important functionality such as branches, jumps, and exceptions. It describes a planned program trace as a collection of instruction scenarios, with exception conditions considered early because they affect transaction properties and constraints. [C5]
VCS constraint solving for microcode stimulus
A Design & Reuse article by AMD and Synopsys authors describes using the Synopsys VCS constraint solver to generate AMD microcode stimuli. The article frames automated random test generators as a response to increasing microprocessor complexity and the declining practicality of hand-written directed tests. It states that such generators create microcode test sequences and emphasize distributing stimuli across meaningful opcode and instruction-attribute values. [C3]
In the described VCS-based approach, SystemVerilog constraint-language constructs provide a concise way to describe possible combinations of microcode instruction attributes and control value distributions for individual fields. The generator architecture has two layers: an upper layer implemented with a SystemVerilog random sequence construct and weighted knobs for high-level distribution control, and a lower opcode-class layer randomized with additional constraints and weights supplied from above. [C3]
The article compares single-class and hierarchical randomization approaches. A single opcode class containing all opcodes was flexible because constraints could be applied across all data members, but it could run slowly because the solver had to process many random variables and a large constraint set; the cited class contained about 100 random variables and 800 constraint equations. The authors then describe an object-oriented hierarchy with a base class for global constraints and derived subclasses for related opcode groups; partitioning constraints into smaller groups reduced memory requirements and improved performance. [C3]
RISC-V verification flow
A RISC-V verification article describes a hybrid methodology that combines constrained-random and directed test generation. It states that constrained-random stimulus from STING can uncover unexpected behaviors, while directed suites such as ImperasTS provide structured compliance and feature coverage. [C4]
In that flow, STING is described as a bare-metal functional verification tool for RISC-V. The source says STING generates portable, self-checking programs for simulation, emulation, FPGA prototypes, and silicon, and that it supports constrained-random and directed stimulus. [C4]
The same article connects the RISC-V flow to several Synopsys-related platforms and tools. It states that tests are portable across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. It also recommends merging ImperasFC/SC results into Verdi and replaying failing cases deterministically in VCS, and it points to Synopsys RISC-V verification resources for STING, ImperasTS, and ImperasDV. [C4]
Verification-lifecycle themes
Across the supplied evidence, Synopsys is characterized by contributions and tools that support reusable, object-oriented, constrained-random verification. The evidence emphasizes stimulus planning, constraint modeling, weighted distribution control, coverage closure, reproducibility through logged seeds and reruns, and portability across simulation, emulation, FPGA prototyping, and silicon validation stages. [C2][C3][C4][C5]