Overview

Top-down stimulus planning is a planning approach for constrained-random processor verification. It is used before or alongside implementation of the stimulus infrastructure to determine what kinds of instruction scenarios, processor states, and exception conditions must be represented so that random stimulus is useful rather than merely syntactically random.

In the cited microprocessor-verification flow, simple random instructions are described as insufficient because they rarely target important processor functionality such as branches, jumps, and exceptions. Constrained-random verification can create more useful stimulus, but only when the stimulus-generation infrastructure contains enough knowledge of the processor instruction set architecture and state. Top-down planning is identified as the activity needed to create that infrastructure.