Scenario Generator

Concept

A scenario generator is a verification testbench component that selects and randomizes scenario objects to produce processor stimulus. In the cited constrained-random verification flow, it can operate over constrained-random, directed-random, and directed scenarios, repeating selection and randomization until a user-specified stopping condition is reached.

First seen 5/28/2026

Last seen 6/5/2026

Evidence 4 chunks

Wiki v1

WIKI

Definition

A scenario generator is a testbench stimulus-generation component that operates on a set of scenario objects. In the described processor verification approach, the generator randomly selects and randomizes one scenario from the available set, then repeats that process until a user-specified condition is reached.[1]

Role in stimulus generation

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NEIGHBORHOOD

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RELATIONSHIPS

10 connections

Directed-Random Stimulus uses → 90% 2e

The scenario generator supports directed random stimulus as one of its scenario types.

Directed Stimulus uses → 90% 2e

The scenario generator supports directed stimulus as one of its scenario types.

Constrained-Random Scenario uses → 95% 2e

The scenario generator works with constrained-random scenarios, selecting and randomizing them to produce stimulus.

Constrained-Random Verification (CRV) ← uses 90% 1e

CRV employs a scenario generator to select and randomize scenarios during stimulus generation.

Instruction Scenario Generation uses → 90% 1e

The scenario generator component works with instruction scenarios and randomizes them.

Processor Testbench ← uses 88% 1e

The processor testbench includes a scenario-generator component to produce stimuli.

Instruction Scenario uses → 95% 1e

The scenario generator works with scenario objects, selecting and randomizing them.

Instruction Scenario Generation ← uses 88% 1e

Instruction scenario generation is driven by a scenario generator that selects and randomizes scenarios.

Directed Random Stimulus uses → 95% 1e

The scenario generator works with directed random stimulus as one type of input.

Directed Test uses → 93% 1e

The scenario generator also works with directed test scenarios loaded from pre-assembled files.

LINKED ENTITIES

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Constrained-Random Scenario USES Extracted graph relationship

Directed Random Stimulus USES Extracted graph relationship

Directed Test USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] A scenario generator works over a set of scenario objects by randomly selecting and randomizing one scenario, repeating until a user-specified condition is reached. Applying constrained-random verification to microprocessors

[2] Test scenarios and the scenario-generator component should be controllable to generate stimuli with varying levels of randomness; SystemVerilog constraints and foreach array constraints can describe instruction-scenario constraints. Applying constrained-random verification to microprocessors

[3] A constrained-random scenario can constrain a long sequence to computational operations, excluding branches, loads, and stores. Applying constrained-random verification to microprocessors

[4] A directed-random scenario can preload data memory with special values, such as walking 0/1 patterns and values near zero or near min/max numbers, before executing arithmetic instructions. Applying constrained-random verification to microprocessors

[5] Directed scenarios can cover specific functionality by reading a pre-assembled program or program trace from a file, including leveraged tests from a processor software team. Applying constrained-random verification to microprocessors

[6] Processor scenario generation must consider boundary conditions for branches, including avoiding cases such as a backward branch that is always taken and ensuring loop-related registers are not modified elsewhere in the loop. Applying constrained-random verification to microprocessors

[7] The described constrained-random verification approach supports directed random and directed stimulus to overcome limitations of traditional directed tests while supporting testbench reuse. Applying constrained-random verification to microprocessors