RISCV-DV

Overview

RISCV-DV is the CHIPS Alliance-hosted chipsalliance/riscv-dv project, described in public repository metadata as a "Random instruction generator for RISC-V processor verification." The same metadata lists Python as the repository language and reports 1,319 stars, 387 forks, and an update timestamp of 2026-07-02T12:12:27Z.^[1]

CHIPS Alliance describes RISCV-DV as an SV/UVM-based framework contributed by Google for rigorous CPU verification. In that description, it is an instruction generator for RISC-V processors and is used to verify features such as privileged modes—machine, supervisor, and user—and trap/interrupt handling.^[2]

The NaxRiscv lockstep-verification paper from RISC-V Summit Europe 2025 cites Google's RISC-V DV as a 2019-era project, with the original repository location given as https://github.com/google/riscv-dv.^[3] The repository subsequently moved to the CHIPS Alliance organization as chipsalliance/riscv-dv.^[2]

Industry reporting on UVM functional coverage for RISC-V cores likewise characterizes RISCV-DV as an open-source project enabling coverage-driven simulation "based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard."^[4]

Verification flow

The supported evidence describes RISCV-DV as a constrained-random instruction-stream or random-binary generator for RISC-V verification. A GLSVLSI 2021 paper characterizes Google's RISC-V DV as a test-generation approach that uses SystemVerilog together with UVM to continuously generate RISC-V instruction streams from constrained-random specifications.^[5]

In the CHIPS Alliance flow description, instructions generated by RISCV-DV are executed both by the core under test and by a reference RISC-V instruction set simulator (ISS), with Spike and Renode named as examples. After execution, the core states are compared after each executed instruction in terms of register writebacks.^[2]

This makes RISCV-DV part of a co-simulation-oriented processor-verification workflow: randomized RISC-V programs provide stimulus, while an ISS supplies a reference execution for comparison against the device under test.^[2] In academic comparisons, RISCV-DV experiments are described as run "using the UVM framework with a commercial simulator," with Spike acting as the golden reference model.^[6]

Supported ISA targets and generated stimuli

A 2025 RISC-V Summit Europe paper on lockstep verification of the NaxRiscv SoC describes RISCV-DV as a robust, open-source framework developed by Google and coded in SystemVerilog/UVM. It is characterized there as a generator of randomized instruction sequences and exhaustive test programs for the RV32/64IMAFDC ISAs across multiple privilege modes (M, S, and U), deliberately targeting critical edge cases to maximize functional coverage.^[7]

The same paper reports that RISCV-DV's generated test programs deliberately target edge cases such as misaligned instructions, register dependencies (RD/RS), pipeline hazards, memory access violations, and unhandled interrupts, thereby probing complex execution paths.^[8]

The paper also notes that RISCV-DV embeds a functional coverage model based on Universal Verification Methodology (UVM), covering various opcodes, extensions (such as F, D, and C), and the proper interactions with control and status registers (CSRs), ensuring exhaustive validation of all ISA features.^[9]

Multi-hart test generation

The ETH Zurich "HARTBREAKER" paper (ISCA 2026) characterizes RISCV-DV as "a widely-used random instruction generator for RISC-V verification" and, to the authors' knowledge, "the only tool capable of automated generation of multi-hart test" cases.^[10] That work used RISCV-DV's "default multi-hart target, configured for 64-bit designs with three harts," evaluating coverage on a triple-hart BOOM configuration.^[11]

RISCV-DV is described in the same comparison as using "pre-defined test scenarios, which guide random programs towards specific features of a CPU," and as lacking capabilities that HARTBREAKER adds—specifically IPI support, memory-model checking, and deterministic interrupt injection—while reaching comparable coverage.^[12]

Implementation and extensibility

The OpenHW Group CORE-V verification documentation describes riscv-dv as implemented as a collection of SystemVerilog classes extending uvm_object. That structure is cited as making it straightforward to extend RISCV-DV classes to modify behavior, including implementing specific instruction streams as extensions of existing RISCV-DV classes rather than modifying RISCV-DV itself.^[13]

COREV-DV is documented as a library of extensions to the Google riscv-dv instruction-stream generator. In the CORE-V flow, a specific RISCV-DV hash can be cloned into a core-specific vendor_lib/riscv-dv directory, and compile makefiles build the required extensions for a core-specific generated test program.^[13]

Use in RISC-V verification projects

CHIPS Alliance states that the RISCV-DV co-simulation setup has been used in verification workflows for multiple RISC-V cores, including VeeR EL2 and Ibex.^[2]

The OpenHW CORE-V verification documentation says core-v-verif mostly uses RISCV-DV "as is," while allowing each core verified in core-v-verif to use whatever RISCV-DV version suits that core's needs.^[13]

NaxRiscv SoC lockstep verification

A 2025 paper from the RISC-V Summit Europe (CEA-LETI) describes a comprehensive lockstep verification framework for the NaxRiscv SoC that integrates RISCV-DV with Verilator-based cycle-accurate RTL simulation, the Spike golden ISS, the RISC-V Lock-Step (RVLS) framework, and Questa/UVM-based coverage analysis. In that flow, RISCV-DV generates constrained-random assembly programs that are executed on SocSim, a Scala-based multi-core SoC simulator built on Verilator, and the results are compared against Spike step-by-step.^[14]

The paper presents the NaxRiscv verification methodology as a multi-layered approach combining directed testing, real-world benchmarking, and constrained-random testing. The constrained-random layer, which leverages RISCV-DV, runs alongside compliance suites such as riscv-tests and riscv-arch-tests and benchmarks such as CoreMark, Dhrystone, FreeRTOS, and the Linux boot stage.^[15]

The same paper reports that the DUT's tracer.log and Spike's spike.log are converted to CSV and processed by Questa to collect coverage into a binary Unified Coverage Database (UCDB), with metrics reported through the vcover report command, covering instruction, CSR, and branch coverpoints including operand registers, branch outcomes, and memory alignment.^[16]

In the NaxRiscv flow, a Jenkins-based CI pipeline automates regression testing and dynamically scales RISCV-DV test generation until predefined coverage targets are met.^[17]

The NaxRiscv paper also reports concrete bugs uncovered through RISCV-DV-driven testing, including:

• Discrepancies in the IO/memory mapping that triggered trap_store_access_fault events.
• A misaligned instruction generated by RISCV-DV that resulted in a malformed opcode and a DUT/ISS mismatch stemming from a lack of verification of the Rd/Rs registers of certain compressed instructions (e.g., C.LWSP), causing trap_load_page_fault events.
• CSR configuration mismatches between the DUT and the Spike golden reference that led to observable execution anomalies (e.g., the DUT missing a trap).^[18]

Other project usage

A 2025 RISC-V Summit Europe abstract on verification of a multi-core RISC-V system reports heavy use of constrained-random testing and random binary generators, "mostly, riscv-dv," to verify designs and uncover bugs. In that project, generated tests were checked using co-simulation with a modified Spike ISS reference model, and code and functional coverage were analyzed to identify corner cases for generator-configuration changes or directed tests.^[19]

The same 2025 abstract reports project-specific modifications to RISCV-DV for full RVV 1.0.0 support, vector memory instruction generation with changing SEW and vector-length values, and additional options to control the kinds of instructions generated. These are described as adaptations by that project, not as evidence of baseline upstream RISCV-DV behavior.^[20]

Evidence limitations

The current evidence supports RISCV-DV's role as a RISC-V constrained-random instruction generator integrated with SV/UVM and ISS-based co-simulation flows, targeting the RV32/64IMAFDC ISA subset across machine, supervisor, and user privilege modes, and as the only tool, to the best of the HARTBREAKER authors' knowledge, capable of automated generation of multi-hart test cases. It does not provide enough detail to document command-line usage, repository license, full supported ISA-extension matrix, output file formats, simulator compatibility matrix, trace formats, or release history.

^[1]: GitHub public context for chipsalliance/riscv-dv. ^[2]: CHIPS Alliance, "SV Tools Project launch," RISCV-DV section. ^[5]: "EPEX: Processor Verification by Equivalent Program Execution," related-work discussion of Google's RISC-V DV. ^[13]: OpenHW Group CORE-V Verification Strategy documentation, "COREV-DV." ^[19]: RISC-V Summit Europe 2025 abstract, "Verification of a RISC-V system with multiple cores." ^[20]: RISC-V Summit Europe 2025 abstract, project-specific RISCV-DV modifications. ^[4]: Semiconductor Engineering, UVM-coverage whitepaper excerpt referencing the Google RISCV-DV open-source project. ^[6]: HARTBREAKER paper, ETH Zurich, RISCV-DV experimental setup description. ^[10]: HARTBREAKER paper, characterization of RISCV-DV as the only tool capable of automated generation of multi-hart tests. ^[11]: HARTBREAKER paper, RISCV-DV default multi-hart target configuration for 64-bit designs with three harts. ^[12]: HARTBREAKER paper, coverage comparison and capabilities RISCV-DV lacks. ^[7]: Ighilahriz & Savry, "Comprehensive lockstep verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM," RISC-V Summit Europe 2025, RISCV-DV description. ^[8]: Ighilahriz & Savry (2025), edge-case targeting description. ^[9]: Ighilahriz & Savry (2025), embedded UVM functional coverage model description. ^[14]: Ighilahriz & Savry (2025), lockstep workflow and tool integration description. ^[15]: Ighilahriz & Savry (2025), multi-level verification strategy description. ^[16]: Ighilahriz & Savry (2025), coverage collection description. ^[17]: Ighilahriz & Savry (2025), Jenkins-based CI description. ^[18]: Ighilahriz & Savry (2025), bug findings from RISCV-DV-driven testing. ^[3]: Ighilahriz & Savry (2025), reference [4] to Google's RISC-V DV, 2019.