RISCV-DV

Overview

RISCV-DV is represented in the supplied public context by the GitHub repository chipsalliance/riscv-dv. The repository is described as a “Random instruction generator for RISC-V processor verification.” The same metadata identifies Python as the repository language and reports 1,308 stars, 385 forks, and an update timestamp of 2026-05-30T08:35:22Z.^[1]

Technical role

Based on the repository description, RISCV-DV’s supported role is to generate random RISC-V instructions for processor verification. The provided evidence supports describing it as a verification stimulus-generation tool, not as a RISC-V processor implementation or simulator.^[1]

Position in RISC-V processor verification research

A USENIX Security 2023 paper on MorFuzz refers to riscv-dv as a “famous constrained instruction generator” and uses it as one of the comparison baselines for evaluating MorFuzz on RISC-V processors.^[2]

In that evaluation, MorFuzz was implemented for the RISC-V architecture and evaluated on three open-source processors: CVA6, Rocket, and BOOM. The paper reports that MorFuzz achieved up to 1.6× more state coverage than riscv-dv, and that MorFuzz reached in about 2.4 hours the coverage that riscv-dv took 24 hours to complete.^[2]

Evidence limitations

The current evidence set does not provide supported details about RISCV-DV command-line usage, generated file formats, license, internal architecture, supported RISC-V extensions, instruction constraints, trace formats, or complete integration flows. Claims about specific vector-instruction features, CI/CD deployments, instruction blacklisting, vsetvli handling, memory-operation stimulus, or scoreboard/reference-model integration have therefore not been included.

^[1]: GitHub public context for chipsalliance/riscv-dv. ^[2]: Xu et al., “MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation,” USENIX Security 2023.