generate_directed_instr_stream function

CodeArtifact

The `generate_directed_instr_stream` function is shown in a DVCon RISCV-DV optimization paper as a parallelized implementation for randomizing directed instruction streams. It computes per-stream insertion counts from configured ratios, forks work into `generate_directed_instr_stream_idx`, assigns thread affinity, joins all forks, validates the final stream length, and shuffles the resulting instruction-stream array.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

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WIKI

Overview

generate_directed_instr_stream is presented in Listing 10 of the DVCon paper Crafting a Million Instructions/Sec RISCV-DV under the heading “Parallelizing Randomization of the Directed Instruction Streams.” The listing shows a function that generates directed RISC-V instruction streams, using forked work items to parallelize stream generation across entries in directed_instr_stream_ratio.[C1]

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riscv-dv part of → 100% 2e

The generate_directed_instr_stream function is part of the RISCV-DV generator.

Directed Instruction Stream Generation implements → 100% 1e

The generate_directed_instr_stream function implements parallel directed instruction stream generation.

CITATIONS

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[1] Listing 10 presents `generate_directed_instr_stream` as a parallelized implementation for randomizing directed instruction streams, including its signature, control flow, fork creation, thread affinity assignment, join behavior, assertion, shuffle, and call to `generate_directed_instr_stream_idx`. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] The RISCV-DV paper identifies directed instruction stream creation and randomization as the highest-impact bottleneck, attributes much of that time to constraint solving, and notes that linear-complexity constraint-solving bottlenecks scale well with multicore parallelization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings