Directed Instruction Stream Generation

Technique

Directed Instruction Stream Generation is a RISCV-DV test-generation technique in which instruction sequences for execution scenarios that require coordinated constraints—such as loops, load/store hazards, and numeric computation exceptions—are generated and randomized as directed streams, then inserted into a non-directed randomized instruction dump while preserving each directed sequence intact.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Directed Instruction Stream Generation is used in RISCV-DV when certain RISC-V instruction categories cannot be meaningfully tested as isolated, unconstrained random instructions. RISCV-DV groups execution use-cases such as loop sequences, load/store hazards, and numeric computation exceptions into directed streams, whose instructions are constrained together as a sequence to create a desired execution scenario. These streams are generated, randomized, and inserted randomly into an initially generated dump of non-directed randomized instructions. During insertion, RISCV-DV avoids inserting one directed stream inside another directed stream already present in the dump. [C1]

Motivation

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RELATIONSHIPS

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riscv-dv ← uses 100% 2e

RISCV-DV categorizes execution use-cases into directed streams that are randomized and inserted into the main dump.

generate_directed_instr_stream function ← implements 100% 1e

The generate_directed_instr_stream function implements parallel directed instruction stream generation.

LINKED ENTITIES

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riscv-dv implemented_in The evidence repeatedly describes directed instruction streams as part of the RISCV-DV generator architecture and implementation.

RISC-V targets The evidence states that RISCV-DV outputs bare-metal RISC-V assembly programs and categorizes RISC-V instruction execution use-cases into directed streams.

CITATIONS

5 sources

5 citations — click to expand

[1] C1: RISCV-DV groups execution use-cases such as loops, load/store hazards, and numeric computation exceptions into directed streams; these streams are constrained as sequences, generated, randomized, and inserted into non-directed randomized instructions while avoiding insertion inside another directed stream. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] C2: RISCV-DV is highly customizable and supports command-line options including the ratio of various instruction-stream kinds to generate. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] C3: Profiling identified directed instruction stream creation and randomization as the highest-impact bottleneck, with most time spent in constraint solvers; the first two listed bottlenecks are linear and handled with multicore parallelization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] C4: Directed-stream insertion into the non-directed stream was identified as a bottleneck with O(n²) complexity; the original merge process picked random insertion locations and retried when a location violated an existing directed sequence. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] C5: Listing 10 shows parallelized directed instruction stream randomization using per-stream insertion counts derived from ratios, forked calls to generate_directed_instr_stream_idx, thread affinity, fork joins, a length assertion, and final shuffling. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings