Instruction Registry

Concept

An instruction registry is the RISCV-DV/eUVM mechanism for registering RISC-V instruction types with the instruction generator. In the eUVM port, registry state and related functions are refactored from static variables into a dedicated `riscv_instr_registry` class to better fit multi-threaded execution and D-language concurrency semantics.

First seen 5/25/2026

Last seen 5/25/2026

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Overview

In the RISCV-DV/eUVM context, the Instruction Registry is a registry mechanism used to register RISC-V instructions with the instruction generator. The eUVM RISCV-DV port introduces a dedicated class named riscv_instr_registry specifically for this purpose, moving registry-related static state and functions out of the original SystemVerilog instruction class implementation.

Purpose

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riscv-dv ← uses 100% 2e

RISCV-DV uses instruction registry to register RISC-V instructions with the generator.

riscv_instr_registry class ← implements 100% 2e

The riscv_instr_registry class implements instruction registration for RISCV-DV in eUVM.

CITATIONS

8 sources

8 citations — click to expand

[1] RISCV-DV SystemVerilog used statically scoped variables in riscv_instr.sv for registering RISC-V instructions with the instruction generator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] The eUVM RISCV-DV port refactors the instruction-registration variables and related functions into a separate class named riscv_instr_registry. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] The registry refactoring supports concurrent execution concerns because global or statically scoped variables accessed by multiple threads require synchronization to avoid race conditions. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] An instance of riscv_instr_registry is created inside singleton riscv_instr_gen_config, preserving the singleton nature of the original static variables. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] RISCV-DV implements each RISC-V ISA instruction as a separate class, leading to hundreds of registered classes. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] The UVM Factory becomes slow when many types are registered because create operations require matching class names against registered class names. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] RISCV-DV uses a custom factory with an instr_registry mapping from riscv_instr_name_t instruction names to qualified class names, and create_instr_list uses the registry to create and template instruction instances. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] RISCV-DV uses riscv_instr_name_t as an enumeration tag for instructions, allowing the custom factory to hash factory objects by enumeration and perform faster matching during instruction-object creation. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings