riscv_instr_registry class
CodeArtifactThe `riscv_instr_registry` class is an eUVM RISCV-DV code artifact created to hold instruction-registration state and related functions that were previously static in `riscv_instr.sv`. It supports RISCV-DV instruction generation by preserving singleton-style registry behavior through an instance stored in `riscv_instr_gen_config`, and it is associated with RISCV-DV’s custom instruction factory approach that avoids slow UVM Factory lookups for large instruction sets.
WIKI
Overview
riscv_instr_registry is a class introduced in the eUVM RISCV-DV port for instruction registry management. The DVCon paper describes that the original RISCV-DV SystemVerilog source had statically scoped variables in riscv_instr.sv used to register RISC-V instructions with the instruction generator. In the eUVM port, those variables and related functions were refactored into a separate class named riscv_instr_registry, specifically for instruction registry functionality. [registry-refactor]
Purpose
NEIGHBORHOOD
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