Overview

In the RISCV-DV/eUVM context, the Instruction Registry is a registry mechanism used to register RISC-V instructions with the instruction generator. The eUVM RISCV-DV port introduces a dedicated class named riscv_instr_registry specifically for this purpose, moving registry-related static state and functions out of the original SystemVerilog instruction class implementation.

Purpose

The original RISCV-DV SystemVerilog code contained statically scoped variables in riscv_instr.sv; these variables served the purpose of registering RISC-V instructions with the instruction generator. In the eUVM port, these variables and their related functions are refactored into the riscv_instr_registry class.

This refactoring addresses concurrency concerns. The cited DVCon paper notes that global or statically scoped variables can hurt runtime efficiency in concurrent software because shared access must be synchronized to avoid race conditions. Encapsulating the instruction-registration state in a class helps align the design with the concurrency semantics of the D programming language used by eUVM.

Singleton placement

Although the registry state is moved out of static variables, the eUVM port preserves the singleton nature of the original SystemVerilog design. An instance of riscv_instr_registry is created inside the singleton riscv_instr_gen_config class, preserving behavior similar to the original static-variable implementation.

Relationship to instruction creation

RISCV-DV implements each RISC-V ISA instruction as a separate class. Because this requires hundreds of instruction classes, registering all of them with the standard UVM Factory would make factory-based creation slow. The paper explains that the UVM Factory supports features such as type and instance overrides, but internally maintains complex data structures and performs class-name matching against registered classes during creation.

To accelerate instruction generation, RISCV-DV uses a custom factory. The custom factory includes an instr_registry mapping in which register(riscv_instr_name_t instr_name, string qualified_name) stores the association between an instruction enum value and a qualified class name. A create_instr_list() routine iterates over the registry, skips unsupported instructions, creates instruction instances, and stores them in instr_template.

Performance characteristic

The custom factory uses the riscv_instr_name_t enumeration to tag each instruction as a numeric value. Because the factory objects are hashed using this enumeration, matching is faster when instruction objects are created than name-based matching through the UVM Factory registration database.