RV32IMAFDC

Concept

RV32IMAFDC is an instruction-set configuration listed as supported by RISCV-DV, an open-source SV/UVM instruction generator for RISC-V processor verification. In the cited RISCV-DV evidence, it is supported alongside RV64IMAFDC and can be used within a verification flow that includes privilege-mode testing, randomized program generation, trap and interrupt handling, debug-mode support, coverage, and co-simulation with multiple instruction-set simulators.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

RV32IMAFDC is listed by RISCV-DV as one of its supported instruction sets, alongside RV64IMAFDC. RISCV-DV is described as an open-source, SystemVerilog/UVM-based instruction generator for RISC-V processor verification.

The provided evidence identifies RV32IMAFDC only as a supported instruction-set target within RISCV-DV; it does not define the internal meaning of the suffix letters in the name.

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NEIGHBORHOOD

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RELATIONSHIPS

1 connections

riscv-dv ← implements 1e

RISCV-DV supports the RV32IMAFDC instruction set.

LINKED ENTITIES

2 links

RV64IMAFDC listed_alongside The evidence lists the supported instruction sets as RV32IMAFDC and RV64IMAFDC.

chipsalliance project_host_or_collaboration_context The evidence states that RISC-V DV is contributed to CHIPS Alliance and describes regular collaboration meetings.

CITATIONS

5 sources

5 citations — click to expand

[1] RV32IMAFDC is listed as a supported instruction set in RISCV-DV, alongside RV64IMAFDC. chipsalliance/riscv-dv

[2] RISCV-DV is an open-source SV/UVM-based instruction generator for RISC-V processor verification. chipsalliance/riscv-dv

[3] RISCV-DV supports privileged modes, page-table randomization, CSR randomization and tests, trap and interrupt handling, MMU stress tests, random program generation, illegal and HINT instruction generation, branch generation, debug-mode support, coverage, testbench handshakes, hand-coded assembly tests, and co-simulation with multiple ISS implementations. chipsalliance/riscv-dv

[4] Running the RISCV-DV instruction generator requires an RTL simulator with SystemVerilog and UVM 1.2 support, and the generator has been verified with VCS, Incisive/Xcelium, Questa, and Riviera-PRO. chipsalliance/riscv-dv

[5] RISC-V DV has been contributed to CHIPS Alliance and is not an officially supported Google product. chipsalliance/riscv-dv