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RV32IMAFDC

Concept WIKI v1 · 5/26/2026

RV32IMAFDC is an instruction-set configuration listed as supported by RISCV-DV, an open-source SV/UVM instruction generator for RISC-V processor verification. In the cited RISCV-DV evidence, it is supported alongside RV64IMAFDC and can be used within a verification flow that includes privilege-mode testing, randomized program generation, trap and interrupt handling, debug-mode support, coverage, and co-simulation with multiple instruction-set simulators.

Overview

RV32IMAFDC is listed by RISCV-DV as one of its supported instruction sets, alongside RV64IMAFDC. RISCV-DV is described as an open-source, SystemVerilog/UVM-based instruction generator for RISC-V processor verification.

The provided evidence identifies RV32IMAFDC only as a supported instruction-set target within RISCV-DV; it does not define the internal meaning of the suffix letters in the name.

Verification context in RISCV-DV

Within RISCV-DV, RV32IMAFDC support is part of a broader RISC-V verification environment. The generator supports machine, supervisor, and user privileged modes; page-table randomization and exceptions; privileged CSR setup randomization; privileged CSR test suites; trap and interrupt handling; MMU stress tests; sub-program generation; random program calls; illegal-instruction and HINT-instruction generation; random forward and backward branches; mixing directed instructions with random instruction streams; debug-mode support with randomized debug ROM; instruction-generation coverage; testbench handshake communication; hand-coded assembly tests; and co-simulation with multiple instruction-set simulators.

Tooling requirements

To run RISCV-DV for supported instruction sets such as RV32IMAFDC, the evidence states that users need an RTL simulator with SystemVerilog and UVM 1.2 support. RISCV-DV has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.

Source and usage notes

The RISCV-DV source can be obtained from GitHub. The evidence describes two usage patterns: developers can run scripts directly with python3, while normal users can install the Python package in editable user mode so that repository changes are immediately available through the run and cov commands.

Collaboration status

The evidence states that RISC-V DV has been contributed to CHIPS Alliance and that regular meetings are held to discuss issues, feature priorities, and development progress. It also notes that RISCV-DV is not an officially supported Google product.

LINKED ENTITIES

2 links
RV64IMAFDC listed_alongside
chipsalliance project_host_or_collaboration_context

CITATIONS

5 sources
5 citations
[1] RV32IMAFDC is listed as a supported instruction set in RISCV-DV, alongside RV64IMAFDC. chipsalliance/riscv-dv
[2] RISCV-DV is an open-source SV/UVM-based instruction generator for RISC-V processor verification. chipsalliance/riscv-dv
[3] RISCV-DV supports privileged modes, page-table randomization, CSR randomization and tests, trap and interrupt handling, MMU stress tests, random program generation, illegal and HINT instruction generation, branch generation, debug-mode support, coverage, testbench handshakes, hand-coded assembly tests, and co-simulation with multiple ISS implementations. chipsalliance/riscv-dv
[4] Running the RISCV-DV instruction generator requires an RTL simulator with SystemVerilog and UVM 1.2 support, and the generator has been verified with VCS, Incisive/Xcelium, Questa, and Riviera-PRO. chipsalliance/riscv-dv
[5] RISC-V DV has been contributed to CHIPS Alliance and is not an officially supported Google product. chipsalliance/riscv-dv