eUVM

Tool

eUVM is a D-language-based verification/testbench environment described in the DVCon paper “Crafting a Million Instructions/Sec RISCV-DV.” In that work, eUVM is used to port and optimize RISCV-DV by enabling multicore testbench execution, refactoring shared/static state, providing profiling support through uvm_trace, and applying low-level performance techniques such as efficient shallow copying and reduced memory allocation.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 13 chunks

Wiki v1

WIKI

Overview

eUVM is presented as a verification environment built on the D Programming Language and used in an optimized RISCV-DV port. The cited work contrasts eUVM with SystemVerilog/UVM in the context of testbench performance, especially where SystemVerilog testbenches lack user-level language constructs for synchronized shared-data access and where multicore simulator support is largely aimed at RTL or gate-level simulation rather than behavioral testbench code. [C1]

Role in RISCV-DV optimization

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RELATIONSHIPS

18 connections

SystemVerilog ← compares with 100% 2e

eUVM is compared with SystemVerilog UVM achieving over 100x speedup.

D Programming Language uses → 100% 2e

eUVM is coded in the D Programming Language.

VIP Level Parallelism uses → 100% 2e

eUVM maps each uvm agent on a separate CPU thread to distribute sequence randomization.

Sequence Level Parallelism uses → 100% 2e

eUVM implements sequence-level parallelization using asynchronous worker threads.

Asynchronous Worker Threads uses → 100% 2e

eUVM implements worker threads as free-running asynchronous threads for parallelism.

TLM Fifo Asynchronous Communication uses → 100% 2e

eUVM implements three types of asynchronous TLM fifos for data exchange between threads.

Parallelized Fork uses → 100% 2e

eUVM allows forking tasks distributed on multiple CPU threads via set_thread_affinity.

Transaction Level Modeling uses → 90% 2e

eUVM supports TLM-based data exchange between components.

riscv-dv ← uses 100% 2e

The parallelized RISCV-DV port is coded in eUVM.

Garbage Collection uses → 100% 2e

eUVM has an automatic garbage collector inherited from the D Programming Language.

Multicore Parallelization uses → 100% 2e

eUVM enables multicore-parallelized UVM testbench implementation.

Functional Coverage uses → 100% 1e

eUVM features functional coverage constructs.

DPI Interface uses → 90% 1e

eUVM integrates with RTL simulators via PLI/VHPI/FLI or DPI interface.

BDD-based Constraint Solving uses → 100% 1e

eUVM uses BDD-based solvers to handle multi-domain constraints of medium complexity.

Discrete Event Simulation uses → 100% 1e

eUVM implements its own discrete-event simulator to schedule testbench tasks and events.

UVM implements → 100% 1e

eUVM is an opensource multicore-enabled implementation of UVM IEEE 1800.2 standard.

SoCFPGA Co-emulation uses → 90% 1e

eUVM testbenches can be executed on SoCFPGA boards for co-emulation.

Context Switching Optimization uses → 90% 1e

eUVM testbenches must avoid frequent context switching to optimize performance.

LINKED ENTITIES

1 links

riscv-dv ported_and_optimized_with The evidence describes an eUVM RISCV-DV port and multiple RISCV-DV optimization techniques implemented in eUVM.

CITATIONS

10 sources

10 citations — click to expand

[1] C1: eUVM is discussed as a D-language-based verification environment in contrast with SystemVerilog/UVM testbench-performance limitations. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] C2: The eUVM RISCV-DV port refactors static RISCV-DV instruction-registry variables into a separate riscv_instr_registry class instantiated from the singleton configuration class. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] C3: eUVM processes can be forked, can execute on multiple cores, and can be delegated to specified processor threads. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] C4: eUVM parallelizes large RISCV-DV instruction randomization by thresholding at par_instr_threshold default 4000 and splitting work across par_num_threads default 8. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] C5: eUVM fork returns a Fork object that can be collected, configured, joined later, and assigned thread affinity through set_thread_affinity. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] C6: Directed instruction-stream randomization in eUVM assigns separate threads to directed-stream groups and uses Fork objects with set_thread_affinity and join. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] C7: eUVM provides uvm_trace for macro-level profiling, but each invocation fetches the current clock time via an operating-system call and can increase runtime if overused. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] C8: eUVM shallow copy uses D object introspection and a memory-slice copy, resulting in a single memcopy operation that is more efficient than element-wise UVM utility copying. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[9] C9: eUVM reduces memory-allocation overhead for formatted strings by using D sformat with caller-provided scratch memory, reducing malloc calls by half in the described example. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[10] C10: The paper motivates eUVM by identifying SystemVerilog/UVM RISCV-DV performance limits, DPI overhead concerns, lack of native data types, limited testbench multicore support, and slower algorithmic execution versus native languages. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings