SoCFPGA Co-emulation

Concept

SoCFPGA co-emulation is a hardware-verification setup enabled by hybrid CPU/FPGA architectures and SoCFPGAs in which the Design under Test is mapped to an FPGA while the testbench continues to run on an HDL simulator. The cited DVCon paper also describes eUVM as portable enough to run on embedded SoCFPGA boards, enabling a mini co-emulation platform with portable stimulus across co-emulation and simulation environments.

First seen 5/25/2026

Last seen 5/25/2026

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Overview

SoCFPGA co-emulation refers to a co-emulation platform enabled by hybrid CPU/FPGA architectures and SoCFPGAs. In the described setup, the Design under Test (DuT) is mapped to an FPGA, while the testbench still runs on an HDL simulator. [C1]

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RELATIONSHIPS

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eUVM ← uses 90% 1e

eUVM testbenches can be executed on SoCFPGA boards for co-emulation.

CITATIONS

8 sources

8 citations — click to expand

[1] SoCFPGA co-emulation platforms are enabled by hybrid CPU/FPGA architectures and SoCFPGAs, with the DuT mapped to an FPGA and the testbench running on an HDL simulator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] Modern HDL simulators can parallelize multicore RTL simulation, but the cited paper says little has been done for multicore testbench parallelization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] SystemVerilog lacks native data types for emulation-platform interfaces and therefore requires C/C++ interaction through DPI, whose data-exchange overhead can adversely affect testbench performance. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] The cited paper states that SystemVerilog lacks fundamental TLM support because integral variables and expressions implicitly hold value-change events, and that computational algorithms in SystemVerilog execute slower than corresponding code in C/C++ or other native languages. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] eUVM is an open-source, multicore-enabled UVM implementation coded in the D programming language. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] eUVM uses a systems-centric top-down approach and provides ABI-level compatibility with C/C++, allowing C/C++ functions to be called from eUVM testbenches and vice versa without runtime overhead. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] eUVM testbenches can be cross-compiled for embedded Linux or Android platforms, including SoCFPGA boards, and an SoCFPGA board can be rendered into a mini co-emulation platform with portable stimulus across co-emulation and simulation environments. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] eUVM integrates with any RTL simulator through PLI, VHPI, FLI, or DPI interfaces and interfaces natively with Verilator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings