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SoCFPGA Co-emulation

Concept WIKI v1 · 5/26/2026

SoCFPGA co-emulation is a hardware-verification setup enabled by hybrid CPU/FPGA architectures and SoCFPGAs in which the Design under Test is mapped to an FPGA while the testbench continues to run on an HDL simulator. The cited DVCon paper also describes eUVM as portable enough to run on embedded SoCFPGA boards, enabling a mini co-emulation platform with portable stimulus across co-emulation and simulation environments.

Overview

SoCFPGA co-emulation refers to a co-emulation platform enabled by hybrid CPU/FPGA architectures and SoCFPGAs. In the described setup, the Design under Test (DuT) is mapped to an FPGA, while the testbench still runs on an HDL simulator. [C1]

Verification context

The cited paper frames SoCFPGA co-emulation against a broader testbench-performance problem: modern HDL simulators can parallelize multicore simulation of RTL designs, but the paper states that comparatively little has been done to enable multicore parallelization of testbenches. [C2]

For SystemVerilog/UVM-based environments, the paper identifies interface and modeling limitations that affect emulation-oriented verification. It states that SystemVerilog lacks native data types, so an interface to an emulation platform requires interaction with C/C++ through the DPI layer; it also notes that DPI data-exchange runtime overhead can adversely affect testbench performance. [C3] The paper further states that SystemVerilog lacks Transaction Level Modeling support at a fundamental level because its integral variables and expressions implicitly carry value-change events, which conflicts with temporal decoupling and contributes to slower algorithmic execution than C/C++ or other native programming languages. [C4]

eUVM-based SoCFPGA board usage

The paper presents eUVM as an open-source, multicore-enabled implementation of UVM coded in the D programming language. [C5] Unlike SystemVerilog UVM, which the paper describes as tightly integrated with RTL simulation, eUVM is described as taking a systems-centric top-down approach and providing ABI-level compatibility with C/C++, allowing C/C++ functions to be called from eUVM testbenches and vice versa without runtime overhead. [C6]

For SoCFPGA co-emulation specifically, the paper states that eUVM testbenches can be cross-compiled for embedded system platforms running Linux or Android, making it feasible to execute eUVM testbenches on embedded boards, including SoCFPGA boards. It further states that an SoCFPGA board can be rendered into a mini co-emulation platform that enables completely portable stimulus across co-emulation and simulation environments. [C7]

Simulator integration

eUVM is described as integrating with any RTL simulator through PLI, VHPI, FLI, or DPI interfaces, and as interfacing natively with Verilator. [C8] This integration is relevant to the SoCFPGA co-emulation flow described in the paper because the co-emulation model keeps the testbench connected to an HDL/RTL simulation environment while the DuT is mapped to FPGA hardware. [C1][C8]

Key characteristics

  • Hardware/software split: the DuT is mapped to an FPGA, while the testbench remains on an HDL simulator. [C1]
  • Embedded-board execution path: eUVM testbenches can be cross-compiled for Linux- or Android-based embedded platforms, including SoCFPGA boards. [C7]
  • Stimulus portability: the cited paper states that an SoCFPGA board can serve as a mini co-emulation platform enabling portable stimulus across co-emulation and simulation environments. [C7]
  • Simulator connectivity: eUVM connects to RTL simulators through PLI/VHPI/FLI/DPI and natively to Verilator. [C8]

CITATIONS

8 sources
8 citations
[1] SoCFPGA co-emulation platforms are enabled by hybrid CPU/FPGA architectures and SoCFPGAs, with the DuT mapped to an FPGA and the testbench running on an HDL simulator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[2] Modern HDL simulators can parallelize multicore RTL simulation, but the cited paper says little has been done for multicore testbench parallelization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[3] SystemVerilog lacks native data types for emulation-platform interfaces and therefore requires C/C++ interaction through DPI, whose data-exchange overhead can adversely affect testbench performance. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[4] The cited paper states that SystemVerilog lacks fundamental TLM support because integral variables and expressions implicitly hold value-change events, and that computational algorithms in SystemVerilog execute slower than corresponding code in C/C++ or other native languages. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[5] eUVM is an open-source, multicore-enabled UVM implementation coded in the D programming language. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[6] eUVM uses a systems-centric top-down approach and provides ABI-level compatibility with C/C++, allowing C/C++ functions to be called from eUVM testbenches and vice versa without runtime overhead. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[7] eUVM testbenches can be cross-compiled for embedded Linux or Android platforms, including SoCFPGA boards, and an SoCFPGA board can be rendered into a mini co-emulation platform with portable stimulus across co-emulation and simulation environments. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[8] eUVM integrates with any RTL simulator through PLI, VHPI, FLI, or DPI interfaces and interfaces natively with Verilator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings