Transaction Level Modeling

Technique

Transaction Level Modeling (TLM) is described in the provided evidence as relying on temporal decoupling of data from simulation time and events. The evidence highlights limitations of SystemVerilog for TLM-style execution and shows how UVM/eUVM TLM FIFOs are used to exchange transaction data between synchronous simulator tasks and asynchronous worker threads.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Transaction Level Modeling (TLM) is a verification and modeling technique whose essential requirement, in the provided evidence, is temporal decoupling: transaction data should be decoupled from simulation time and events. This characteristic is contrasted with SystemVerilog behavior, where integral variables and expressions implicitly carry value-change events, enabling constructs such as wait(a > b) and thereby tying data values to event semantics. [C1]

SystemVerilog implications

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RELATIONSHIPS

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eUVM ← uses 90% 2e

eUVM supports TLM-based data exchange between components.

CITATIONS

6 sources

6 citations — click to expand

[1] C1: TLM requires temporal decoupling of data from simulation time and events, while SystemVerilog integral variables and expressions implicitly hold value-change events; the evidence reports SystemVerilog algorithms as an order of magnitude slower than corresponding C/C++ or native-language code. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] C2: Testbench parallelization is less developed than multicore RTL simulation, and SystemVerilog/UVM testbenches require synchronized shared-data access constructs because they are behavioral, support automatic scoping, and can share data by reference. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] C3: A regular UVM TLM FIFO blocks reads when empty and writes when full using explicit events associated with its ports; writes can trigger the read event to reactivate a blocked task. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] C4: eUVM worker threads are free-running asynchronous threads decoupled from the scheduler; because they cannot wait for simulator events, eUVM implements asynchronous TLM FIFO mechanisms for synchronized exchange with other threads. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] C5: An async-write TLM FIFO supports worker-thread-generated UVM transactions transferred to a regular UVM task by using a software semaphore when full and read-port event triggering when a transaction is put into an empty FIFO; async-read handles the reverse direction. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] C6: Transaction-based acceleration for co-emulation is described as proposing an untimed hardware verification language domain to accelerate the testbench while the design under test is mapped to FPGA and the testbench runs on an HDL simulator. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings