Sequence Level Parallelism

Technique

Sequence Level Parallelism is a testbench optimization technique described for eUVM that exploits multicore concurrency in UVM-style verification environments, especially simple module-level testbenches with limited UVM components. It uses free-running worker threads, asynchronous TLM FIFOs, and multicore-distributed forked tasks to parallelize transaction generation and sequence processing.

First seen 5/25/2026

Last seen 5/25/2026

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Overview

Sequence Level Parallelism is described as a technique for taking advantage of multicore concurrency in simple module-level testbenches that may contain only a limited number of UVM components. The technique appears in the context of eUVM optimization for RISCV-DV-style testbench workloads, where parallelization is applied below or within the sequence-generation layer rather than only by mapping large VIP components to different executors. [C1]

Motivation

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eUVM ← uses 100% 2e

eUVM implements sequence-level parallelization using asynchronous worker threads.

TLM Fifo Asynchronous Communication uses → 100% 2e

Sequence level parallelism uses TLM fifos for data exchange between worker threads and synchronous tasks.

Asynchronous Worker Threads uses → 100% 1e

Sequence level parallelism is achieved using free-running asynchronous worker threads.

CITATIONS

8 sources

8 citations — click to expand

[1] C1: Sequence Level Parallelization is introduced as a technique for taking advantage of multicore concurrency in simple module-level testbenches, and VIP-level mapping may be suboptimal due to scheduler behavior and load-balancing issues. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] C2: eUVM worker threads are free-running asynchronous threads owned by the simulator, decoupled from the scheduler, unable to wait for events, and able to trigger events. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] C3: Worker threads share memory with tasks, but UVM data exchange is handled through TLM FIFOs; standard TLM FIFOs use events to block empty reads and full writes. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] C4: eUVM implements asynchronous TLM FIFO variants for async write, async read, and async read/write use cases, using semaphores where asynchronous worker threads cannot wait on simulator events. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] C5: eUVM worker thread constructs can parallelize a UVM sequencer by creating free-running worker threads that feed a virtual sequencer in round-robin fashion, useful when transaction generation and randomization are complex and time-consuming. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] C6: eUVM provides a multicore-parallelized fork for scenarios where asynchronous TLM FIFO overhead would offset gains for simple transactions, and eUVM can distribute forked tasks across CPU threads associated with multiple task executors. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] C7: For sequences containing thousands of transactions in a queue or array, eUVM can slice the sequence container and split slices across forked tasks, with each fork processing a slice. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] C8: The eUVM parallelized fork listing shows fork objects being stored, lambda wrapping for scoped-variable capture, use of set_thread_affinity to bind forks to task executors, and join semantics where forks execute after join or another blocking construct. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings