Crafting a Million Instructions/Sec RISCV-DV
Paper“Crafting a Million Instructions/Sec RISCV-DV” is a technical paper by Puneet Goel, Ritu Goel, and Jyoti Dahiya on accelerating RISCV-DV, an open-source RISC-V random instruction generator, through a parallelized Embedded UVM implementation and other high-performance-computing techniques. The paper reports a multicore UVM testbench implementation capable of generating millions of constrained-randomized RISC-V instructions per second, over 100× faster than the original SystemVerilog UVM RISCV-DV implementation.
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Overview
“Crafting a Million Instructions/Sec RISCV-DV” is a paper subtitled “HPC Techniques to Boost UVM Testbench Performance by Over 100x.” The listed authors are Puneet Goel of Incore Semiconductors, and Ritu Goel and Jyoti Dahiya of Coverify Systems Technology. The paper focuses on improving the performance of RISCV-DV, described in the paper as an open-source random instruction generator widely used for functional verification of RISC-V cores. [C1][C2]
The paper presents a parallelized RISCV-DV port coded in Embedded UVM (eUVM) and explores techniques for improving testbench performance. Its abstract reports a multicore UVM testbench implementation that generates millions of constrained-randomized RISC-V instructions per second, achieving a speedup of over 100× compared with the original RISCV-DV implementation coded in SystemVerilog UVM. [C3]
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