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Constrained Random Verification (CRV)

Concept

Constrained Random Verification (CRV) is a verification methodology that generates randomized input stimuli subject to explicit constraints, with the goal of reaching meaningful and coverage-relevant behaviors. In RISC-V verification, CRV is exemplified by RISC-V DV, which uses SystemVerilog/UVM constraints for instruction-stream generation and can be evaluated with coverage statistics and mutation testing.

First seen 5/28/2026
Last seen 6/7/2026
Evidence 10 chunks
Wiki v2

WIKI

Overview

Constrained Random Verification (CRV) is a verification approach centered on generating input stimuli under constraints so that verification runs exercise useful or targeted areas of a system's behavior space. A cited problem in CRV is producing stimuli that achieve good coverage of targeted behavioral corners, while many existing approaches do not provide formal guarantees about the distribution of the generated system runs.

In processor verification, CRV is used to generate processor-level stimuli such as randomized instruction streams. Reported processor-level stimulus-generation techniques include combinations of model-based methods with constraint solving, coverage-guided generation using Bayesian networks or other machine-learning methods, fuzzing, symbolic execution, and RISC-V-specific randomized instruction generation.

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections
riscv-dv ← implements 100% 2e
RISC-V DV is a CRV framework implementing constrained random verification for RISC-V.
Constraint-Based Randomization uses → 97% 2e
CRV leverages constraint-based randomization as its core technique for generating test stimuli.
Program Trace uses → 93% 1e
CRV uses the program trace as the main stimulus for the DUT.
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← uses 100% 1e
The paper is centered on constrained random verification for RISC-V.
Constrained Random Generation (CRG) uses → 100% 1e
CRG is a central building block of a CRV framework.
Functional Coverage uses → 95% 1e
CRV tracks and utilizes coverage information to measure verification progress.
Stimulus Generation uses → 97% 1e
CRV uses stimulus generation infrastructure to produce useful test stimuli for processor verification.
simulation-based verification ← uses 85% 1e
Simulation-based verification uses CRV as a core test generation approach.
Instruction Scenario uses → 93% 1e
CRV uses instruction scenarios as structured building blocks for test stimulus.

LINKED ENTITIES

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Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion USES Extracted graph relationship
riscv-dv IMPLEMENTS Extracted graph relationship
Constrained Random Generation (CRG) USES Extracted graph relationship
Functional Coverage USES Extracted graph relationship
simulation-based verification USES Extracted graph relationship

CITATIONS

8 sources
8 citations — click to expand
[1] CRV focuses on generating constrained input stimuli to obtain good coverage of targeted behavior-space corners, and existing CRV solutions may lack formal distribution guarantees. On Uniformly Sampling Traces of a Transition System (Extended Version)
[2] Processor-level verification approaches include model-based methods with constraint solving, coverage-guided generation using Bayesian networks or other machine-learning techniques, fuzzing, symbolic execution, and RISC-V-specific randomized instruction generation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[3] RISC-V DV uses SystemVerilog/UVM constraints as the foundation for test generation, and an efficient coverage-guided loop would require dynamic evolution of constraint descriptions at runtime. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[4] The RISC-V DV evaluation used coverage information such as register-access statistics and immediate-field access, unique-value, and percent-covered measurements. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[5] The RISC-V CRV paper is based on the RISC-V DV framework and uses mutation-based testing techniques to assess test-generation quality. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[6] The RISC-V DV experiments indicated effectiveness in finding common implementation bugs. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[7] Listed future directions include broader mutation evaluation, RTL and ISS/RTL cross-level evaluation, coverage-feedback integration, support for instruction-set extensions, and extra-functional uses such as resiliency, information-flow tracking, and side-channel evaluation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[8] CRV and coverage-driven methodologies can rely on time-consuming simulation regressions and manual constraint adjustment to reach coverage goals. Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach