Constrained Random Generation (CRG)

Concept

Constrained Random Generation (CRG) is a powerful and scalable test generation technique that specifies and solves constraints to produce new tests in a structured manner. It serves as a central building block of Constrained Random Verification (CRV) frameworks, yielding better results than pure randomized generation while enabling coverage tracking to measure verification progress and quality.

First seen 6/7/2026

Last seen 6/7/2026

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Constrained Random Generation (CRG)

Definition

Constrained Random Generation (CRG) is a powerful and scalable test generation technique that has been shown to be very effective in many different application areas. Rather than relying on fully random stimulus, CRG works by specifying and solving constraints to generate new tests in a structured approach, yielding better results than pure randomized generation.

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RELATIONSHIPS

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riscv-dv ← implements 95% 1e

RISC-V DV uses CRG as a central building block for its test generation.

Constrained-Random Verification (CRV) ← uses 100% 1e

CRG is a central building block of a CRV framework.

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Constrained-Random Verification (CRV) USES Extracted graph relationship

CITATIONS

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[1] Constrained Random Generation (CRG) is a powerful and scalable test generation technique. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[2] CRG has been shown very effective in many different application areas, including functional verification, validation of power management functionality, and error resiliency evaluations. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[3] CRG is a central building block of a Constrained Random Verification (CRV) framework, and it works by specifying and solving constraints to generate new tests in a structured approach, yielding better results than pure randomized generation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[4] Coverage information is tracked and utilized to measure the verification progress as well as assess the verification quality. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[5] RISC-V DV is a powerful CRV framework, actively developed by Google, that implements CRG by leveraging SystemVerilog and UVM to generate tests in assembly format based on randomized instruction streams. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[6] RISC-V DV supports the complete 32 and 64 bit standard instruction set extensions, executes each generated test on a reference system and the system under test (high-level simulator or RTL core), and compares their outputs to enable a comprehensive end-to-end verification flow. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion