Constrained Random Generation (CRG)

Concept WIKI v1 · 6/7/2026

Constrained Random Generation (CRG) is a powerful and scalable test generation technique that specifies and solves constraints to produce new tests in a structured manner. It serves as a central building block of Constrained Random Verification (CRV) frameworks, yielding better results than pure randomized generation while enabling coverage tracking to measure verification progress and quality.

Constrained Random Generation (CRG)

Definition

Constrained Random Generation (CRG) is a powerful and scalable test generation technique that has been shown to be very effective in many different application areas. Rather than relying on fully random stimulus, CRG works by specifying and solving constraints to generate new tests in a structured approach, yielding better results than pure randomized generation.

Role in Verification Flows

CRG is a central building block of a Constrained Random Verification (CRV) framework. Within a CRV flow:

Tests are generated by specifying and solving constraints over the space of valid stimuli.
Coverage information is tracked during the run and is utilized to measure the verification progress as well as to assess the verification quality.

By combining constraint-based generation with coverage feedback, CRV (powered by CRG) can direct stimulus generation toward hard-to-reach corner cases and report meaningful progress metrics.

Application Areas

According to the literature, CRG has been demonstrated as effective in a range of application areas, including:

Functional verification of hardware designs.
Validation of power management functionality.
Error resiliency evaluations.

Concrete Implementations

RISC-V DV is a powerful CRV framework, actively developed by Google and tailored for RISC-V, that implements Constrained Random Generation. It leverages SystemVerilog and the Universal Verification Methodology (UVM) to generate tests in assembly format based on randomized instruction streams, supporting the complete 32- and 64-bit standard RISC-V instruction set extensions. Generated tests are executed on both a reference system and the system under test (a high-level simulator or RTL core), and the outputs are compared to enable an end-to-end verification flow. RISC-V DV is designed as a configurable framework that can be adapted to different verification needs.

Relationship to Constrained Random Verification (CRV)

While CRG focuses on the generation step — producing valid, structured stimuli by solving constraints — it is normally embedded inside a larger Constrained Random Verification (CRV) methodology, which adds the surrounding infrastructure for self-checking, reference comparison, coverage collection, and result analysis.

LINKED ENTITIES

2 links

riscv-dv IMPLEMENTS

Constrained-Random Verification (CRV) USES

CITATIONS

6 sources

6 citations

[1] Constrained Random Generation (CRG) is a powerful and scalable test generation technique. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[2] CRG has been shown very effective in many different application areas, including functional verification, validation of power management functionality, and error resiliency evaluations. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[3] CRG is a central building block of a Constrained Random Verification (CRV) framework, and it works by specifying and solving constraints to generate new tests in a structured approach, yielding better results than pure randomized generation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[4] Coverage information is tracked and utilized to measure the verification progress as well as assess the verification quality. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[5] RISC-V DV is a powerful CRV framework, actively developed by Google, that implements CRG by leveraging SystemVerilog and UVM to generate tests in assembly format based on randomized instruction streams. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[6] RISC-V DV supports the complete 32 and 64 bit standard instruction set extensions, executes each generated test on a reference system and the system under test (high-level simulator or RTL core), and compares their outputs to enable a comprehensive end-to-end verification flow. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion