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Constrained Random Verification (CRV)

Concept WIKI v2 · 6/7/2026

Constrained Random Verification (CRV) is a verification methodology that generates randomized input stimuli subject to explicit constraints, with the goal of reaching meaningful and coverage-relevant behaviors. In RISC-V verification, CRV is exemplified by RISC-V DV, which uses SystemVerilog/UVM constraints for instruction-stream generation and can be evaluated with coverage statistics and mutation testing.

Overview

Constrained Random Verification (CRV) is a verification approach centered on generating input stimuli under constraints so that verification runs exercise useful or targeted areas of a system's behavior space. A cited problem in CRV is producing stimuli that achieve good coverage of targeted behavioral corners, while many existing approaches do not provide formal guarantees about the distribution of the generated system runs.

In processor verification, CRV is used to generate processor-level stimuli such as randomized instruction streams. Reported processor-level stimulus-generation techniques include combinations of model-based methods with constraint solving, coverage-guided generation using Bayesian networks or other machine-learning methods, fuzzing, symbolic execution, and RISC-V-specific randomized instruction generation.

Relationship to coverage and constraints

CRV uses constraints to shape random generation toward valid or interesting verification scenarios. In the RISC-V DV framework, SystemVerilog/UVM constraints are described as the foundation for test generation. The cited RISC-V CRV evaluation also identifies a coverage-feedback loop as a future direction: coverage information could guide instruction-stream generation toward coverage goals, but doing so efficiently would require dynamically evolving constraint descriptions at runtime.

Coverage is therefore both a measurement target and a potential driver for CRV. In the RISC-V DV evaluation, coverage information included register-access statistics and immediate-field coverage. For example, the reported immediate-field table counted accesses and unique values for SHAMT, I-immediate, S-immediate, B-immediate, J-immediate, and U-immediate fields, with percentage-of-possible-values coverage ranging from 100% for SHAMT to much smaller percentages for larger immediate spaces.

RISC-V DV as an example

RISC-V DV is presented in the cited paper as the basis for an overview, evaluation, and discussion of CRV for RISC-V. The evaluation used mutation-based testing techniques, inspired by software mutation testing, to assess test-generation quality. The authors report that their experiments indicate RISC-V DV is effective in finding common implementation bugs.

The paper also lists several RISC-V DV test strategies, including arithmetic-only testing, random instruction stress testing, jump-stress testing, and loop testing. This illustrates how a CRV environment can combine randomization with named strategies that emphasize particular instruction classes or control-flow patterns.

Limitations and research directions

The evidence identifies several open or future directions for CRV in the RISC-V setting:

  • broader evaluation with more mutation classes and more test iterations;
  • evaluation not only on an instruction-set simulator (ISS), but also on RTL cores and ISS/RTL cross-level settings;
  • integration of coverage information into the generation loop;
  • designated support for RISC-V instruction-set extensions by generating appropriate constraint classes and integrating new generators with existing ones;
  • use of RISC-V DV beyond functional verification, including error-resiliency evaluation, information-flow tracking, and side-channel evaluation, which require suitable test-generation techniques and coverage metrics.

Position in verification practice

CRV is closely related to coverage-driven and simulation-based verification flows. A public study on coverage-driven verification notes that CRV and coverage-driven methodologies can rely on time-consuming and redundant simulation regressions, and that manual effort may be needed to adjust constraints and steer stimuli toward coverage objectives. Another public source proposes formal trace-sampling methods to address the lack of distribution guarantees in CRV-style stimulus generation.

LINKED ENTITIES

5 links
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion USES
riscv-dv IMPLEMENTS
Constrained Random Generation (CRG) USES
Functional Coverage USES
simulation-based verification USES

CITATIONS

8 sources
8 citations
[1] CRV focuses on generating constrained input stimuli to obtain good coverage of targeted behavior-space corners, and existing CRV solutions may lack formal distribution guarantees. On Uniformly Sampling Traces of a Transition System (Extended Version)
[2] Processor-level verification approaches include model-based methods with constraint solving, coverage-guided generation using Bayesian networks or other machine-learning techniques, fuzzing, symbolic execution, and RISC-V-specific randomized instruction generation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[3] RISC-V DV uses SystemVerilog/UVM constraints as the foundation for test generation, and an efficient coverage-guided loop would require dynamic evolution of constraint descriptions at runtime. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[4] The RISC-V DV evaluation used coverage information such as register-access statistics and immediate-field access, unique-value, and percent-covered measurements. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[5] The RISC-V CRV paper is based on the RISC-V DV framework and uses mutation-based testing techniques to assess test-generation quality. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[6] The RISC-V DV experiments indicated effectiveness in finding common implementation bugs. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[7] Listed future directions include broader mutation evaluation, RTL and ISS/RTL cross-level evaluation, coverage-feedback integration, support for instruction-set extensions, and extra-functional uses such as resiliency, information-flow tracking, and side-channel evaluation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[8] CRV and coverage-driven methodologies can rely on time-consuming simulation regressions and manual constraint adjustment to reach coverage goals. Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach

VERSION HISTORY

v2 · 6/7/2026 · gpt-5.5 (current)
v1 · 5/28/2026 · gpt-5.5