Bug hunting SoC designs to achieve full functional coverage closure
PaperFirst seen 7/1/2026
Last seen 7/1/2026
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34 connectionsThe paper uses randomized delay injection between transactions.
The paper uses regression testing to validate bugs and achieve coverage.
The paper describes using constrained random verification to verify SoC designs.
The paper contrasts directed verification with constrained random verification.
The paper uses functional coverage as sign-off criterion.
The paper describes a test environment for random stimulus generation and coverage.
The paper uses AXI protocol as one of the SoC protocols for stimulus generation.
The paper describes cache coherency scenarios as part of verification.
The paper addresses stashing as a specific verification scenario involving L1/L2 cache.
The paper uses backdoor access for efficient register reading and data comparison.
The paper uses front door access for writing to DUT registers via the physical bus.
The paper describes coverage-driven verification as the final phase of random verification.
The paper identifies cross coverage as part of functional coverage implementation.
The paper describes writing a generic stimulus base class for protocol-specific derivation.
The paper targets coverage closure as the goal of constrained random verification.
The paper describes automating test pattern generation by dynamically changing transaction parameters.
The paper describes stashing data in L1/L2 cache as a verification scenario.
The paper uses constraint-based stimulus generation to push DUT into corner cases.
The paper uses weight-based transaction control for managing transaction types.
The paper uses data comparison via backdoor read to uncover front-door path bugs.
The paper uses unaligned address testing as a specific verification scenario.
The paper verifies bus arbitration by checking system bus behavior with multiple simultaneous masters.
The paper uses AXI transaction ID randomization to generate unordered transactions.
The paper uses seed-based regression grading to prioritize scenarios that contribute to coverage.
The paper uses SystemVerilog for functional and constraint verification.
The paper uses parameters.txt to pass random parameters at simulation time.
The paper uses the random_axi stimulus class derived from the stimulus base class.
Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming mentions → 100% 1e
The paper cites this reference as related work.
The paper cites this reference as related work.
The paper cites this reference as related work.
The paper cites this reference as related work.
Vijeta Marwah is listed as an author of the paper on bug hunting SoC designs.
The paper evaluates SoC designs through constrained random verification.
Saurabh Mishra is listed as an author of the paper on bug hunting SoC designs.