Cache Coherency

Concept

Cache coherency in the provided evidence is treated as a cross-cutting concern spanning (a) multiprocessor microarchitectural verification (cache coherency protocols, false sharing, traffic diversity), (b) SoC functional-coverage closure (Scenario #5 - cache coherency and stashing, read-sharing between cores, read-sharing between cores and IO masters), (c) instruction-cache coherence as a hardware-security property in RISC-V processors (FENCE.I, Ariane Bugs B1/B4, CWE-1202), (d) heterogeneous CPU-FPGA coherency (ECI's symmetric and asymmetric protocols, I/O cache coherence options on SoC-FPGAs), and (e) commercial verification tooling (Breker's Cache Coherency TrekApp 2.0, RV64 MultiCore MoesiStates with planned cache state transitions, false-share memory stress tests, and CMN/Coherent Mesh Network bug classes). Recent evidence shows real bugs at the system level: Coherent Mesh Network programming errors, misconfigured ARM CMN pins, and deadlocks from common cache line access.

First seen 6/2/2026

Last seen 7/6/2026

Evidence 10 chunks

Wiki v4

WIKI

Cache Coherency

Overview

In the provided evidence, cache coherency appears in several related roles:

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

Cache Coherency TrekApp 2.0 ← implements 98% 2e

Cache Coherency TrekApp 2.0 is specifically designed to implement cache coherency testing.

SBVer ← evaluates 90% 2e

SBVer targets cache coherency in multiprocessor configurations as part of its verification scope.

MTPG ← evaluates 90% 1e

MTPG is a portable test generator for cache-coherent multiprocessors.

Stashing ← part of 90% 1e

Stashing is part of the broader cache coherency verification scenario.

MOESI Cache States ← part of 92% 1e

MOESI cache states are part of cache coherency protocols tested in the RV64 multi-core verification.

Bug hunting SoC designs to achieve full functional coverage closure ← uses 95% 1e

The paper describes cache coherency scenarios as part of verification.

MPVer ← evaluates 100% 1e

MPVer is designed to verify cache coherency protocols in multiprocessor systems.

LINKED ENTITIES

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Cache Coherency TrekApp 2.0 IMPLEMENTS Extracted graph relationship

MOESI Cache States PART_OF Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] High-performance microprocessors perform cache coherency in multiprocessor configurations and present a complex external interface that is challenging to verify; MPVer and SBVer are described as code generators targeting multiprocessor behavior, sharing patterns (false sharing, true data sharing), and traffic diversity. Bug hunting SoC designs to achieve full functional coverage closure

[2] SoC functional-coverage methodology defines Scenario #5 (cache coherency and stashing), read sharing between cores, and read sharing between core and IO masters, together with randomized AXI transaction IDs and back-to-back latency checks. Bug hunting SoC designs to achieve full functional coverage closure

[3] ECI is an FPGA-side customizable cache-coherency stack supporting both symmetric and asymmetric protocols on a two-socket CPU-FPGA architecture; existing FPGA deployments are typically non-cache-coherent or asymmetric. ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures

[4] Modern heterogeneous SoC-FPGA platforms support multiple I/O cache coherence options between CPUs and FPGAs; appropriate selection and software/hardware modifications improved performance by an average of 20%. Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device

[5] RISC-V FENCE.I enforces instruction-cache coherence; TheHuzz found Bugs B1 and B4 in Ariane around FENCE.I semantics and classifies the violation as CWE-1202; an unprivileged-software exploit leverages the bug to cause instruction-cache incoherence via a contrived safe JIT compiler. TheHuzz: Instruction Fuzzing of Processors Using Golden Reference

[6] The Breker SystemVIP Library includes a Cache Coherency TrekApp 2.0 alongside RISC-V and ARM System Integrity TrekApps, Firmware-First, Power Management, Security, and Networking TrekApps. RISC-V Core & SoC Verification (Breker, 2024)

[7] Breker's RV64 MultiCore MoesiStates test set exercises planned MOESI cache state transitions on RISC-V multicore designs; it is paired with atomics testing, Dekker memory ordering, and false-share memory stress tests (free-running write/check loops over 1000 iterations). RISC-V Core & SoC Verification (Breker, 2024)

[8] Real coherency bugs found in production designs include Coherent Mesh Network (CMN) programming issues, misconfigured ARM CMN pin to enable coherent traffic, and a deadlock triggered by common cache line access; Breker compares typical directed coherency coverage against its automated coherency tests using a SystemVIP test-suite synthesis coverage comparison. RISC-V Core & SoC Verification (Breker, 2024)