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Constrained-random testing

Technique WIKI v1 · 6/25/2026

Constrained-random testing is a hardware verification technique in which randomized stimuli are biased, via constraints, toward interesting, hard-to-reach, and yet-untested design logic. Constraints are typically written manually to direct randomness, but as verification progresses most generated tests yield diminishing coverage gains. Open-source generators such as RISCV-DV implement constrained-random test generation for RISC-V processor verification, producing assembly programs that target edge cases like misaligned instructions, register dependencies, pipeline hazards, memory access violations, and unhandled interrupts.

Constrained-random testing

Overview

Constrained-random testing is one of the most widely adopted methods for generating stimuli for simulation-based hardware verification. Randomness provides test diversity, but tests tend to repeatedly exercise the same design logic. To address this, constraints — typically written manually — are used to bias random tests toward interesting, hard-to-reach, and yet-untested logic in the design under test (DUT).

Motivation and limitations

As verification progresses, most constrained-random tests yield little to no effect on functional coverage. Because stimuli generation typically consumes significantly fewer resources than simulation, a more effective approach involves randomly generating a large number of tests, selecting the most effective subset, and simulating only that subset. This motivates learning-based selection methods such as coverage-directed test selection and novelty-driven verification that bias test selection toward stimuli likely to increase functional coverage.

Implementation in practice (RISC-V verification)

In the context of RISC-V processor verification, the open-source tool RISCV-DV implements constrained-random test generation. It is described as a tool that "automatically generates constrained-random assembly programs" which "deliberately target edge cases — such as misaligned instructions, register dependencies (RD/RS), pipeline hazards, memory access violations, and unhandled interrupts — thereby probing complex execution paths."

RISCV-DV is an open-source instruction stream generator for RISC-V processors, part of Google's DV project aimed at providing a complete verification infrastructure for RISC-V cores. It is built on an SV/UVM infrastructure and supports a wide range of RISC-V extensions including RV32IMAFDC and RV64IMAFDC instruction sets, multiple privileged modes (Machine, Supervisor, and User), page table randomization, privileged Control Status Register (CSR) setup randomization, trap/interrupt handling, and more. The system can be customized via YAML files. Generated instructions are fed to both an Instruction Set Simulator (ISS) and the DUT, with outputs compared at the end of simulation.

Integration with verification frameworks

Constrained-random testing via RISCV-DV is typically integrated into multi-level verification strategies alongside directed testing, real-world benchmarking, and lockstep co-simulation. In the NaxRiscv SoC lockstep verification framework, RISCV-DV-driven constrained-random test generation is synchronized with cycle-accurate Verilator simulation and Spike-based functional co-simulation through the RISC-V Lock-Step (RVLS) framework, with coverage analysis powered by Questa/UVM. A Jenkins-based CI pipeline automates regression testing and dynamically scales RISCV-DV test generation until predefined coverage targets are met.

Related approaches

  • Coverage-Directed Test Selection (CDTS): a supervised-learning approach that learns from coverage feedback to bias selection toward tests with a high probability of increasing functional coverage.
  • Novelty-Driven Verification: learns to identify and simulate stimuli that differ from previously simulated stimuli, reducing the number of required simulations.
  • Hybrid Intelligent Testing: combines CDTS and Novelty-Driven Verification to address the limitations of each method individually.

LINKED ENTITIES

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riscv-dv IMPLEMENTS

CITATIONS

6 sources
6 citations
[1] Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification, where constraints (typically written manually) bias random tests toward interesting, hard-to-reach, and yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[2] As verification progresses, most constrained random tests yield little to no effect on functional coverage, motivating approaches that randomly generate many tests and simulate only an effective subset. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[3] RISCV-DV automatically generates constrained-random assembly programs that target edge cases such as misaligned instructions, register dependencies (RD/RS), pipeline hazards, memory access violations, and unhandled interrupts. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM
[4] RISCV-DV is an open-source instruction stream generator, part of Google's DV project, built on SV/UVM, supporting RV32IMAFDC/RV64IMAFDC, multiple privileged modes, page-table randomization, CSR setup randomization, and trap/interrupt handling, configurable via YAML files. Reinforcement Learning Framework for RISC-V Functional Verification
[5] The NaxRiscv verification framework integrates RISCV-DV-driven constrained-random test generation with cycle-accurate Verilator simulation, Spike golden-model co-simulation, and Questa/UVM coverage analysis, synchronized through the RISC-V Lock-Step (RVLS) framework. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM
[6] A Jenkins-based CI pipeline automates regression testing and dynamically scales RISCV-DV test generation until predefined coverage targets are met. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM