Coverage-guided Aging

Coverage-guided aging

Technique

Coverage-guided aging is a processor-verification technique that feeds runtime functional-coverage information from an ISS back to an endless randomized RISC-V instruction stream generator, with the goal of making generated instruction coverage more uniform over time.

First seen 6/3/2026

Last seen 9/22/2026

Evidence 10 chunks

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WIKI

Overview

Coverage-guided aging is a runtime guidance technique for cross-level processor verification. It is used with an endless randomized instruction stream generator in a co-simulation setup where an RTL processor is checked against an Instruction Set Simulator (ISS). The technique tracks and updates coverage information in the ISS and dynamically feeds that information back to the instruction stream generator so that the generated instructions have a more uniform coverage distribution over time [1].

The approach was presented as part of work on RISC-V processor verification, where the authors describe it as a novel concept used to smooth out the coverage distribution of randomized instruction streams over time [2].

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← introduces 100% 3e

The DATE 2022 work proposes a novel cross-level verification approach that employs the new concept of coverage-guided aging.

Functional Coverage implements → 90% 2e

Coverage-guided Aging implements functional coverage monitoring to guide instruction generation.

Coverage-Observer ← implements 95% 2e

The Coverage-Observer implements the Coverage-guided Aging mechanism.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 95% 2e

The cross-level verification approach applies coverage-guided aging to guide generation and even out coverage over time.

RISC-V Processor Verification with Coverage-guided Aging ← uses 90% 1e

The paper employs the coverage-guided aging concept to steer instruction generation and smooth coverage distribution.

RISC-V instruction stream generator ← uses 80% 1e

Coverage-guided aging feedback guides the generator to achieve a more uniform instruction distribution over time.

Instruction Coverage Points uses → 90% 1e

Coverage-guided Aging uses instruction coverage points to determine which instruction combinations need more testing.

LINKED ENTITIES

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RISC-V Processor Verification with Coverage-guided Aging USES Extracted graph relationship

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging INTRODUCES Extracted graph relationship

RISC-V instruction stream generator USES Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] Coverage-guided aging tracks and updates ISS coverage information and feeds it back to an instruction stream generator to make generated instructions more uniformly distributed. [PDF] RISC-V Processor Verification with Coverage-guided Aging*

[2] The technique was presented as a novel concept for smoothing the coverage distribution of randomized instruction streams over time. [PDF] RISC-V Processor Verification with Coverage-guided Aging*

[3] The approach is used in a cross-level verification setting with an RTL processor and an ISS reference model, producing one endless instruction stream at runtime. [PDF] RISC-V Processor Verification with Coverage-guided Aging*

[4] Simple endless randomized instruction streams without runtime coverage feedback are limited in their ability to continuously achieve broad and deep coverage. [PDF] RISC-V Processor Verification with Coverage-guided Aging*

[5] The Coverage-Observer monitors ISS state, samples executed instructions, maps them to coverage points, performs coverage aging, and provides hints when functionality must be covered again. Cross-Level Processor Verification via

[6] In the reported implementation, coverage points are defined as the cross-product of instruction groups. Cross-Level Processor Verification via

[7] The Instruction-Injector evaluates Coverage-Observer hints and injects instructions while considering different fetch behavior and execution timing between cores. Cross-Level Processor Verification via

[8] The Comparator compares ISS and RTL register values by logging value changes and comparing changes at the same position, stopping the simulation on a difference. Cross-Level Processor Verification via

[9] A core adapter handles RTL microarchitectural effects by filling addresses not fetched by the ISS with randomized values and forwarding them to the RTL core. Cross-Level Processor Verification via

[10] The case study used a 32-bit pipelined MINRES The Good Core RISC-V core, the SystemC-based RISC-V VP2 ISS, Verilator, RV32IMCZicsrZifencei configuration, and an Ubuntu 20.04 LTS/Ryzen 7 PRO 4750U/36 GB RAM setup with a one-second SystemC simulation limit. Cross-Level Processor Verification via

[11] The DATE 2022 paper is bibliographically identified as 'Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging' by Bruns, Herdt, Jentzsch, and Drechsler. A RISC-V Test Sequences Generation Method Based on Instruction ...