Coverage-guided Aging

Coverage-guided aging

Technique

Coverage-guided aging is a verification technique used in cross-level processor verification to drive randomized instruction stream generation toward uncovered functional coverage points by progressively aging (forgetting) recently hit coverage targets.

First seen 6/3/2026

Last seen 6/25/2026

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Overview

Coverage-guided aging is a randomized test-generation guidance strategy for cross-level processor verification. It directs an endless randomized instruction stream generator to repeatedly revisit functional coverage targets that have not been exercised recently, rather than allowing the generator to settle on a fixed distribution of stimuli [1]. The technique was introduced for comparing an instruction-set simulator (ISS) and a register-transfer level (RTL) processor core running side by side, where the goal is to expose functional divergences between the two models.

Context: Cross-Level Processor Verification

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← introduces 100% 2e

The paper introduces Coverage-guided Aging as a novel technique for cross-level processor verification.

Functional Coverage implements → 90% 2e

Coverage-guided Aging implements functional coverage monitoring to guide instruction generation.

Coverage-Observer ← implements 95% 2e

The Coverage-Observer implements the Coverage-guided Aging mechanism.

Instruction Coverage Points uses → 90% 1e

Coverage-guided Aging uses instruction coverage points to determine which instruction combinations need more testing.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 95% 1e

Incorporates coverage-guided aging to improve exploration during verification.

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

CITATIONS

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[1] Coverage-guided aging is a guidance mechanism used in cross-level processor verification to drive endless randomized instruction stream generation toward uncovered or aged functional coverage points. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)

[2] The Coverage-Observer measures functional coverage from the ISS execution state, performs coverage-aging, and hints the Instruction-Injector when functionality must be covered again; coverage points are defined as the cross-product of instruction groups. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)

[3] The Instruction-Injector evaluates hints from the Coverage-Observer and injects instructions to cover the requested functionality, accounting for differing fetch behaviors and execution timings between the ISS and the RTL core. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)

[4] The Comparator logs register-value changes from the ISS and the RTL core and continuously matches them at the same position; on any difference, the simulation is terminated. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)

[5] The evaluation used the 32-bit pipelined MINRES The Good Core (TGC) RISC-V core against the RISC-V VP2 ISS via a Verilator-generated C++ model in a SystemC test bench, configured for RV32IMCZicsrZifencei on Ubuntu 20.04 LTS with a one-second SystemC simulation time limit (~20 million instructions). Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)

[6] The paper situates coverage-guided aging among related approaches including constraint-based specification generation, coverage-guided fuzzing of ISSes, directed RISC-V test suites, and formal model-checking methods, noting scalability concerns for the latter. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-Guided Aging (DATE 2022)