RISC-V instruction stream generator

Tool

A randomized, coverage-guided instruction stream generator tailored for RISC-V that produces an endless, unrestricted instruction stream at runtime. It is used in cross-level RTL processor verification, coupled with an Instruction Set Simulator (ISS) as a functional reference model and guided by runtime coverage information (including coverage-guided aging) to achieve a broader and more uniform test coverage over time.

First seen 9/22/2026

Last seen 9/22/2026

Evidence 2 chunks

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WIKI

RISC-V instruction stream generator

A RISC-V instruction stream generator is a randomized, coverage-guided test-generation component tailored to the RISC-V Instruction Set Architecture (ISA). It is designed to produce an endless, unrestricted instruction stream at runtime for use in cross-level processor verification, where an RTL processor core is checked against an Instruction Set Simulator (ISS) used as a functional reference model.

Background and motivation

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RELATIONSHIPS

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RISC-V Processor Verification with Coverage-guided Aging ← uses 85% 1e

The approach leverages a custom RISC-V instruction stream generator as part of the verification setup.

Endless randomized instruction stream generation implements → 90% 1e

The custom generator produces a single endless instruction stream at runtime, embodying the endless randomized generation technique.

Coverage-guided Aging uses → 80% 1e

Coverage-guided aging feedback guides the generator to achieve a more uniform instruction distribution over time.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 75% 1e

The approach centers on a randomized coverage-guided instruction stream generator.

LINKED ENTITIES

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RISC-V Processor Verification with Coverage-guided Aging USES Extracted graph relationship

Endless randomized instruction stream generation IMPLEMENTS Extracted graph relationship

Coverage-guided Aging USES Extracted graph relationship

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] The generator produces an endless and unrestricted instruction stream that evolves dynamically at runtime based on observed coverage information. RISC-V Processor Verification with Coverage-guided Aging

[2] The setup supports arbitrary combinations of load/store and CSR instructions as well as infinite loops, unlike earlier instruction stream generators. RISC-V Processor Verification with Coverage-guided Aging

[3] Coverage information is continuously updated based on the execution state of the ISS and used to provide feedback to the instruction stream generator. RISC-V Processor Verification with Coverage-guided Aging

[4] Coverage-guided aging is employed to smooth out the coverage distribution of the randomized instruction stream over time. RISC-V Processor Verification with Coverage-guided Aging

[5] The approach was evaluated on the 32-bit pipelined RISC-V core of the MINRES The Good Core (TGC) series and demonstrated a much more regular coverage distribution. RISC-V Processor Verification with Coverage-guided Aging

[6] The generator is described in detail in the DATE 2022 paper 'Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging' by Bruns, Herdt, Jentzsch, and Drechsler. RISC-V Processor Verification with Coverage-guided Aging

[7] Google's open-source RISC-V DV framework uses co-simulation with an ISS as a functional reference model and SystemVerilog constraint-based specification techniques to generate RISC-V assembly tests one after another. RISC-V Processor Verification with Coverage-guided Aging

[8] Prior RISC-V DV generators based on simple randomized test strategies do not collect or employ runtime coverage information, making it difficult to continuously achieve a broad and deep test coverage in endless instruction streams. RISC-V Processor Verification with Coverage-guided Aging