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RISC-V Processor Verification with Coverage-guided Aging

Paper
First seen 9/22/2026
Last seen 9/22/2026
Evidence 3 chunks

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RELATIONSHIPS

9 connections
Coverage-guided Aging uses → 90% 1e
The paper employs the coverage-guided aging concept to steer instruction generation and smooth coverage distribution.
RISC-V instruction stream generator uses → 85% 1e
The approach leverages a custom RISC-V instruction stream generator as part of the verification setup.
Endless randomized instruction stream generation uses → 80% 1e
The paper's generator produces an endless randomized instruction stream during runtime.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging derived from → 90% 1e
The extended abstract summarizes prior work presented in the DATE 2022 paper.
riscv-dv mentions → 90% 1e
The paper discusses the RISC-V DV framework as a prominent approach in the context of RISC-V verification.
riscv-torture mentions → 85% 1e
The paper cites the riscv-torture test generator in its references.
Coverage-Guided Fuzzing mentions → 90% 1e
The paper lists coverage-guided fuzzing among related techniques used to generate tests.
Symbolic Execution mentions → 90% 1e
The paper mentions symbolic execution as a technique to find specific inputs in related work.
Constraint-based specification mentions → 85% 1e
The paper discusses constraint-based specifications in the context of RISC-V instruction sets and verification approaches.