RISC-V Torture
ToolRISC-V Torture is a RISC-V testcase generator and test project, published as the Scala GitHub repository ucb-bar/riscv-torture. In the DATE 2019 paper “Verifying Instruction Set Simulators using Coverage-guided Fuzzing,” it is used as a baseline against RISC-V ISA tests and a coverage-guided fuzzer; the paper characterizes Torture tests as randomly generated, valid instruction sequences that do not use execution feedback.
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Overview
RISC-V Torture is a RISC-V test-generation tool. The public repository is ucb-bar/riscv-torture, described as “RISC-V Torture Test” and implemented primarily in Scala.
In the DATE 2019 paper “Verifying Instruction Set Simulators using Coverage-guided Fuzzing,” RISC-V Torture is integrated as the “RISC-V Torture testcase generator” in an evaluation comparing directed RISC-V ISA tests, Torture-generated tests, and a coverage-guided fuzzing approach for instruction set simulator verification.
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