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STIMSMITH

DIG (Dynamic Instruction Generator)

Tool
First seen 7/1/2026
Last seen 7/1/2026
Evidence 1 chunks

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RELATIONSHIPS

12 connections
Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States ← introduces 100% 1e
The paper introduces DIG as a novel Dynamic Instruction Generator.
Dynamic Instruction Generation implements → 100% 1e
DIG implements the technique of dynamic instruction generation by leveraging processor runtime states.
Instruction Set Simulator uses → 100% 1e
DIG accesses processor runtime information via an instruction set simulator to produce valid instruction streams.
Processor Runtime Architectural State uses → 100% 1e
DIG leverages processor runtime architectural states to generate valid instruction streams.
Intra-instruction Test Knowledge uses → 100% 1e
DIG incorporates intra-instruction test knowledge to enhance instruction stream quality.
Inter-instruction Test Knowledge uses → 100% 1e
DIG incorporates inter-instruction test knowledge to enhance instruction stream quality.
VeeR EH2 evaluates → 100% 1e
DIG is evaluated through a case study using Western Digital's open-source RISC-V core VeeR EH2.
riscv-dv compares with → 100% 1e
DIG is compared against RISC-V DV, showing a 62.50% reduction in test instructions.
riscv-torture compares with → 100% 1e
DIG is compared against RISC-V Torture, showing an 86.11% reduction in test instructions.
Functional Verification implements → 90% 1e
DIG is designed to enhance functional verification of processors.
Functional Coverage uses → 100% 1e
DIG aims to achieve superior functional coverage with compact test instruction streams.
Test Instruction Stream uses → 100% 1e
DIG generates test instruction streams as its primary output for verification.