Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
PaperFirst seen 7/1/2026
Last seen 7/1/2026
Evidence 2 chunks
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16 connectionsThe paper references CSP-based test generation as related work.
Anlin Liu is listed as a corresponding author of the paper affiliated with Zhejiang University.
T.C. Lu is listed as an author affiliated with Zhejiang University.
Yuhao Xi is listed as an author affiliated with Zhejiang University.
Yangfan Liu is listed as an author affiliated with HEXIN Technologies Co., Ltd.
Peng Liu is listed as an author affiliated with Zhejiang University.
The paper focuses on enhancing functional verification of processors.
The paper mentions random instruction generators as the state-of-the-art baseline for comparison.
The paper references MicroGP as a related evolutionary assembly program generator.
The paper references Genesys-Pro as a related test program generation tool.
The paper references coverage directed test generation using Bayesian networks as related work.
The paper references Bayesian networks for coverage directed test generation as related work.
The paper references MicroGP as an evolutionary assembly program generator in related work.
The paper references SMT-solver state generation for testing as related work.
The paper introduces DIG as a novel Dynamic Instruction Generator.
The paper references a work on revealing RISC processor dark instructions and vulnerabilities.