Bayesian Networks for Test Generation

Technique

A coverage-directed test generation technique for processor functional verification in which Bayesian networks are used to guide the generation of instruction streams toward uncovered functional points. It is referenced as prior art by the DIG paper, which proposes an alternative dynamic instruction generation approach that exploits processor runtime architectural states.

First seen 7/1/2026

Last seen 7/1/2026

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Overview

Bayesian Networks for Test Generation is a coverage-directed test generation (CDG) technique used in the functional verification of processors. The approach uses Bayesian networks to model dependencies between test-generation parameters and coverage feedback, steering the generation of instruction streams toward portions of the design space that remain uncovered.

Origin in Functional Verification

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Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States ← mentions 90% 1e

The paper references Bayesian networks for coverage directed test generation as related work.

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Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States MENTIONS Extracted graph relationship

CITATIONS

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[1] Bayesian Networks for Test Generation is a coverage-directed test generation technique used in functional verification of processors. Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States

[2] The seminal publication for the technique is Fine and Ziv, 2003, 'Coverage directed test generation for functional verification using bayesian networks' (doi:10.1145/775832.775907). Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States

[3] The DIG paper (Liu et al., 2024) cites the Bayesian-network technique as related prior work in coverage-directed test generation and proposes a complementary runtime-state-driven approach. Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States

[4] The DIG paper situates Bayesian-network-based test generation alongside other established approaches including constraint-satisfaction formulations (Bin et al., 2002), evolutionary generators such as MicroGP (Squillero, 2005), Genesys-Pro (Adir et al., 2004), abstract-CSP generation (Katz et al., 2012), SMT-solver-based generation (Campbell & Stark, 2015), and MicroTESK (Chupilko et al., 2017). Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States