coverage-directed test generation

Technique

Coverage-directed test generation (CDG) is a test-generation technique that uses coverage feedback to steer new tests toward unexercised behavior, such as unexplored RTL regions, code branches, or model states. It is used in domains including hardware verification and robotic-software simulation, and contrasts with unguided random testing, which can repeatedly exercise the same functionality.

First seen 5/28/2026

Last seen 6/8/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Coverage-directed test generation (CDG) is a test-generation technique in which coverage information is used as feedback to steer the generation or selection of additional tests. In hardware verification, the motivation is to reach uncovered RTL regions or code branches automatically rather than relying only on manual constraint tuning or unguided random tests. Public examples also describe CDG systems that use large language models to generate Verilog stimuli for unexplored code branches, and reinforcement learning to explore behavioral models using rewards based on coverage feedback.

Relationship to random testing

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random instruction generation uses → 80% 1e

Coverage-directed test generation builds on random instruction generation to address coverage gaps.

pre-silicon verification part of → 85% 1e

Coverage-directed test generation was proposed to overcome limitations of random instruction generation in verification.

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CITATIONS

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[1] Random instruction generators are commonly used in processor verification because they require limited human expertise and scale to large RTL designs. ProcessorFuzz: Processor Fuzzing with Control and

[2] Unguided random instruction generation can produce repetitive inputs that exercise the same processor functionality, reducing bug-finding chances. ProcessorFuzz: Processor Fuzzing with Control and

[3] Manual adjustment of constraints to target uncovered RTL regions increases engineering effort and slows verification. ProcessorFuzz: Processor Fuzzing with Control and

[4] TheHuzz uses coverage metrics such as statement, branch, line, and expression coverage, but prior work discussed in the evidence considers these metrics insufficient by themselves for processor verification. ProcessorFuzz: Processor Fuzzing with Control and

[5] Hardware-to-software-model fuzzing can use software-fuzzer coverage metrics such as basic-block and edge coverage, but introduces the challenge of proving equivalence between the hardware design and software model. ProcessorFuzz: Processor Fuzzing with Control and

[6] VerilogReader integrates an LLM into coverage-directed test generation, using it to understand Verilog code logic and generate stimuli for unexplored code branches. VerilogReader: LLM-Aided Hardware Test Generation

[7] The VerilogReader public summary reports that the framework outperforms random testing on designs within the LLM's comprehension scope and proposes prompt-engineering optimizations. VerilogReader: LLM-Aided Hardware Test Generation

[8] In robotic-software testing for human-robot interaction simulations, reinforcement learning has been used to automate BDI-model exploration with a reward function based on coverage feedback, leading to effective coverage-directed test generation. Intelligent Agent-Based Stimulation for Testing Robotic Software in Human-Robot Interactions