Instruction Set Simulator
ToolAn Instruction Set Simulator (ISS) is used as the reference model in the cited coverage-guided processor-verification flow, where it is co-simulated with an RTL RISC-V core and compared through register/output behavior.
First seen 5/25/2026
Last seen 5/29/2026
Evidence 8 chunks
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Overview
An Instruction Set Simulator (ISS) is used in the cited processor-verification work as the reference side of a co-simulation environment. In the evaluation case study, the Device Under Test is the open-source RISC-V VexRiscv RTL processor, while the reference ISS is extracted from the open-source RISC-V VP. The paper describes RISC-V VP as a SystemC TLM virtual prototype that supports many RISC-V instruction sets. [C1]
Role in co-simulation
NEIGHBORHOOD
2 nodes · 1 edgesgraph · Instruction Set Simulator · depth=1
RELATIONSHIPS
2 connectionsAn ISS is used as a reference model for the RTL processor under test.
The ISS simulates instruction set architecture behavior as a reference model.
CITATIONS
7 sources7 citations — click to expand
[1] The ISS is used as the reference model in the evaluation, extracted from RISC-V VP, while VexRiscv is the RTL DUT; RISC-V VP is described as a SystemC TLM virtual prototype supporting many RISC-V instruction sets. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] The RTL core is translated to C++ with Verilator and embedded with the ISS into a common SystemC testbench. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] The execution controller receives register information from the RTL core and ISS, and the flow distinguishes equal behavior from behavior mismatches, terminating execution with an error on mismatch. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] The whole co-simulation, including the RTL core and ISS, is instrumented for coverage, and coverage plus return code are fed back to the fuzzer. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] A custom post-processing co-simulation logs executed instructions with corresponding addresses for clustering test vectors that expose the same bug. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] The co-simulation overview and translation-buffer example show ISS and RTL instruction/address coordination through a translation buffer. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[7] The evaluation uses the RV32IM configuration of VexRiscv, and the fuzzing approach includes CSR instruction insertion/replacement in write-then-read pairs to make CSR misbehavior detectable through registers by the execution controller. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing