Overview
Cross-level testing is presented as a processor verification approach based on an on-the-fly, endless instruction stream. In the cited RISC-V work, the testbench feeds this stream to both an RTL core under test and an Instruction Set Simulator (ISS) reference model inside a co-simulation setup.
Co-simulation execution model
The co-simulation testbench is implemented in SystemC. It places the RTL core on one side and the ISS reference model on the other, with a test controller orchestrating execution. The controller repeatedly:
- lets the RTL core execute one instruction;
- lets the ISS execute the same instruction;
- compares the RTL and ISS execution states, especially registers;
- reports an error if the states mismatch, or continues until the testing time is exhausted.
This instruction-by-instruction comparison makes the method a tightly coupled form of processor co-simulation: divergence is detected at the point where the compared architectural state no longer agrees.
Instruction-stream handling
The approach generates instructions during simulation rather than relying on a precompiled finite test program. Instruction fetching is driven by the program counter. When the RTL core fetches an instruction, the instruction stream generates a new instruction and records it with the corresponding program counter. When the ISS fetches, it receives the corresponding instruction fetched by the RTL side. The paper describes this as an endless instruction stream and states that it is generated without restrictions on the generated instructions.
Memory and interface structure
The RTL core is clock-driven and has separate instruction-memory and data-memory interfaces. The testbench uses memory interfaces that translate between RTL core signals and TLM transactions, giving the RTL core and ISS a unified memory abstraction. The ISS also uses separate instruction and data memory interfaces.
For data memory, the described implementation is lazy: it starts empty, stores data on writes, and on reads either returns previously stored data or generates new random data if the address has not been accessed before. The RTL and ISS data memories use the same random seed, so they behave identically when the RTL core and ISS perform the same data-memory access sequence in the same order.
Role in processor verification
Within the cited work, cross-level testing connects a low-level RTL implementation with a higher-level executable reference model. Its main mechanism is state comparison between the implementation and the ISS after each instruction, supported by SystemC/TLM infrastructure and on-the-fly instruction generation.