Register Value Comparison

Concept

Register value comparison is a cross-level processor-verification technique that compares the architectural register values of an ISS and an RTL-core to detect functional mismatches. The cited approach performs comparisons only after real register-value changes and after the corresponding instruction has completed, reducing false mismatches and avoiding unnecessary performance overhead.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 2 chunks

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Overview

Register value comparison is used to determine whether two processor implementations exhibit equal behavior by comparing their register files. In the cited cross-level verification flow, it is used to compare an ISS with an RTL-core and to detect functional mismatches when their register values differ. [C1]

Purpose in processor verification

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RELATIONSHIPS

3 connections

Execution Controller ← uses 100% 2e

The Execution Controller compares register values to detect mismatches between processor cores.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 2e

The paper uses register value comparison as the mechanism to detect functional mismatches between ISS and RTL-core.

Co-Simulation ← uses 95% 1e

The co-simulation uses register value comparison to detect functional mismatches.

CITATIONS

7 sources

7 citations — click to expand

[1] Register value comparison realizes behavioral equality checking between processors and detects mismatches when register values differ. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] Important processor functionality eventually leads to a register value change, such as an add instruction writing its result to a destination register. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] Register values should be compared or logged immediately after the relevant instruction has completely executed to avoid false mismatches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] Complete instruction execution is easy to detect for an ISS but difficult for a pipelined RTL processor because there is no general completion signal. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] Frequent register comparison can degrade performance, so comparison should occur only when a register value has changed. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] The Execution Controller detects processor-core mismatches and performs register value comparison when it detects a register value change. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[7] In the example, the RTL-core erroneously executes an LWU instruction and changes x8 while the ISS changes x6, causing register value comparison to detect a mismatch and stop the simulation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing