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Register Value Comparison

Concept WIKI v1 · 5/26/2026

Register value comparison is a cross-level processor-verification technique that compares the architectural register values of an ISS and an RTL-core to detect functional mismatches. The cited approach performs comparisons only after real register-value changes and after the corresponding instruction has completed, reducing false mismatches and avoiding unnecessary performance overhead.

Overview

Register value comparison is used to determine whether two processor implementations exhibit equal behavior by comparing their register files. In the cited cross-level verification flow, it is used to compare an ISS with an RTL-core and to detect functional mismatches when their register values differ. [C1]

Purpose in processor verification

The technique is motivated by the observation that important processor functionality eventually produces a change in a register value. For example, an add x1, x2, x3 instruction reads registers x2 and x3, adds the values, and writes the result to x1; therefore, comparing register values can expose functional mismatches between processor implementations. [C2]

Timing and synchronization

Register values must be compared at the correct execution point. The cited work states that register values should be compared or logged right after the processor cores have completely executed the relevant instruction. This requires instruction-execution synchronization; otherwise, comparisons may report false mismatches. [C3]

This synchronization is straightforward for an ISS but difficult for a pipelined RTL processor, because a pipelined processor parallelizes execution and has no general signal indicating complete instruction execution. [C4]

Change-triggered comparison

The approach avoids comparing registers too frequently because doing so degrades performance. Comparisons are unnecessary when no register value changed. For example, add x0, x2, x3 does not change a register value because register x0 remains zero. Therefore, the cited approach performs register value comparison only when a register value was really changed, using those changes as synchronization and comparison time points. [C5]

Role of the Execution Controller

In the cited verification flow, an Execution Controller detects processor-core mismatches. When it observes a register value change, it executes a register value comparison between the ISS and RTL-core registers. If the register values are not equal, the mismatch is treated as an error and the simulation is stopped. [C6]

Example mismatch scenario

The cited example uses an RV32I setting in which the ISS raises an illegal-instruction exception for LWU x8, x0, 48, because LWU is not an RV32I instruction, and later changes register x6 while executing trap-handler instructions. In contrast, the example RTL-core erroneously executes the LWU instruction and changes register x8. The Execution Controller detects the register-value change, compares the ISS and RTL-core registers, discovers the mismatch between x8 and x6, throws an error, and stops the simulation. [C7]

CITATIONS

7 sources
7 citations
[1] Register value comparison realizes behavioral equality checking between processors and detects mismatches when register values differ. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] Important processor functionality eventually leads to a register value change, such as an add instruction writing its result to a destination register. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] Register values should be compared or logged immediately after the relevant instruction has completely executed to avoid false mismatches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] Complete instruction execution is easy to detect for an ISS but difficult for a pipelined RTL processor because there is no general completion signal. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] Frequent register comparison can degrade performance, so comparison should occur only when a register value has changed. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] The Execution Controller detects processor-core mismatches and performs register value comparison when it detects a register value change. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[7] In the example, the RTL-core erroneously executes an LWU instruction and changes x8 while the ISS changes x6, causing register value comparison to detect a mismatch and stop the simulation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing