Constrained Randomization

Concept

Constrained randomization is a verification methodology in which random stimuli are generated subject to user-defined constraints, allowing tests to focus on interesting input regions while still exercising a broad design space. It is most commonly associated with SystemVerilog's rand variables and constraint blocks, where the randomize() method produces values that satisfy a constraint expression. The technique is foundational to modern functional verification flows, including UVM, and is being progressively implemented in open-source simulators such as Verilator via translation of SystemVerilog constraints to SMT-LIB2.

First seen 7/8/2026

Last seen 7/8/2026

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Constrained Randomization

Overview

Constrained randomization is a stimulus-generation methodology used in functional verification of digital designs. Instead of applying purely unconstrained random values to a design under test (DUT), the verification engineer declares a set of variables as random (rand in SystemVerilog) and writes constraints that restrict the legal values those variables may take. Calling randomize() then produces values that satisfy every constraint, giving the testbench random but valid stimuli ^[1]. The technique concentrates simulation effort on inputs considered useful and interesting, allowing verification regressions to converge faster than naive random testing ^[1].

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SystemVerilog ← implements 1e

SystemVerilog implements constrained randomization functionality for digital design verification.

Verilator ← implements 1e

Verilator now implements constrained randomization as introduced by Antmicro.

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SystemVerilog IMPLEMENTS Extracted graph relationship

Verilator IMPLEMENTS Extracted graph relationship

CITATIONS

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9 citations — click to expand

[1] Constrained randomization uses random variables together with constraints to generate valid but random stimuli for verification. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[2] SystemVerilog expresses constrained randomization with rand class fields and constraint blocks solved by randomize(). Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[3] Verilator implements constrained randomization by converting SystemVerilog expressions to SMT-LIB2 and delegating to Z3/cvc5. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[4] Sub-expressions are formatted via $sformatf and constant folding collapses nested formatting into a single call filled at randomize-time. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[5] SMT-LIB2 signedness is conveyed via operators such as bvslt (signed less than) and bvult (unsigned less than). Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[6] Verilator forces a random hash of output bits via an extra assert to introduce entropy and obtain truly random solutions from deterministic SMT solvers. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[7] Arrays, state-dependent/conditional constraints, and 1-bit-vs-boolean distinctions remain unsupported in Verilator's constrained-randomization implementation. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[8] NOVA coordinates coverage-aware test selection with Bayes-optimized constrained randomization, achieving up to 2.82× coverage convergence speedup. NOVA: Coordinated Test Selection and Bayes-Optimized Constrained Randomization for Accelerated Coverage Closure

[9] Python verification environments such as cocotb and cocotb-coverage can provide constrained randomization and coverage. Effective Design Verification -- Constrained Random with Python and Cocotb