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Verilator

Tool WIKI v5 · 6/25/2026

Verilator is an open-source SystemVerilog simulator and lint system. It compiles Verilog/SystemVerilog designs into optimized, potentially multithreaded C++/SystemC models that run faster than interpreted simulation. Verilator is used as the RTL simulation backend in several hardware-fuzzing and verification frameworks (including ProcessorFuzz, RFuzz, DirectFuzz, and FuSS), and is the basis for ongoing work on UVM testbench support via the uvm-verilator project.

Verilator

Overview

Verilator is an open-source SystemVerilog simulator and lint system. Its public GitHub repository is verilator/verilator. [citation: Verilator is an open-source SystemVerilog simulator and lint system]

According to the surrounding evidence, Verilator compiles Verilog or SystemVerilog code into an optimized, potentially multithreaded model wrapped in a C++/SystemC module. These compiled models are reported to execute faster than normal SystemC code and faster than traditional interpreted simulators, with the tool claiming performance on par with or better than many closed-source simulators. [citation: Verilator compiles Verilog/SystemVerilog into optimized C++/SystemC models]

Role in hardware fuzzing frameworks

Verilator is used as the RTL simulation backend in multiple hardware-fuzzing and verification frameworks described in the evidence:

  • ProcessorFuzz: Verilator is used for RTL simulation of all evaluated processor designs in ProcessorFuzz. ProcessorFuzz performs differential testing by running an ISA simulation as a golden reference model and an RTL simulation, then comparing the results; for inputs deemed interesting based on coverage, ProcessorFuzz launches the RTL simulation and compares the resulting extended RTL trace log against an extended ISA trace log generated by an extended Spike ISA simulator. A difference between the two logs is treated as a potential processor-design bug. [citation: ProcessorFuzz uses Verilator for RTL simulation; ProcessorFuzz RTL simulation and trace comparison]
  • RFuzz: RFuzz uses Verilator for one of its two main fuzzing approaches (the other being FPGA-accelerated). The fuzzer communicates with the DUT via buffers in shared memory, and Verilator simulates the DUT on the CPU side of the SoC. [citation: RFuzz uses Verilator for DUT simulation]
  • DirectFuzz: DirectFuzz builds on RFuzz and likewise uses Verilator to simulate the hardware design, while adding directed-fuzzing capabilities that focus fuzzing on specific submodules of a larger system. [citation: DirectFuzz uses Verilator like RFuzz]
  • FuSS: FuSS uses Verilator to convert hardware models into cycle-accurate software models for simulation. Verilator serves as the backend of the FuSS framework due to its precise modeling of synthesizable Verilog designs; FuSS is described as compatible with any compiled simulator that supports cycle-accurate execution. [citation: FuSS uses Verilator to convert hardware models into cycle-accurate software models]
  • Cascade: The Cascade artifact (USENIX Security 2024) requires a specific Verilator version (v5.006) and provides an explicit reinstall procedure if the running container produces an unknown-warning error (-Wno-EOFNEWLINE). [citation: Cascade artifacts use Verilator v5.006]

UVM testbench support

Long-running efforts to enable UVM testbenches in Verilator are being driven by Antmicro, Wilson Snyder, and contributors from the open-source RTL design community. These efforts have been organized under the uvm-verilator project and have converged into milestones including support for upstream UVM 2017 in Verilator. UVM is described as a popular digital design verification method integrated with many pre-existing workflows, tools, and verification IP, and bringing UVM to Verilator is presented as a step toward a fully open-source ASIC development flow. [citation: UVM support in Verilator via uvm-verilator]

Within the CHIPS Alliance SV Tools Project, Verilator is also referenced as one of the tools whose SystemVerilog feature support is tracked by the sv-tests suite and its interactive dashboard. [citation: sv-tests tracks Verilator SV support]

Verilator in the RISC-V verification landscape

A survey of RISC-V processor verification discusses Verilator in the context of open-source RISC-V cores and their verification flows, noting that the tool is part of the broader open-source verification ecosystem alongside efforts such as RVVI-Trace, RVVI-VVP, and RISCV-DV. [citation: Verilator in RISC-V verification survey]

Relationship to RTL simulation

The evidence consistently describes Verilator as an open-source RTL simulator used as the simulation backend in multiple fuzzing and verification frameworks, where it produces RTL traces or state that are compared against a golden reference (typically an ISA simulation) for differential testing. [citation: Verilator as open-source RTL simulator]

Evidence boundaries

The DATE 2022 cross-level processor-verification excerpt includes https://www.veripool.org/verilator/ as a referenced URL, but the excerpt does not provide enough surrounding detail to support a stronger claim about how Verilator was used in that work. [citation: DATE 2022 excerpt references Verilator URL only]

LINKED ENTITIES

3 links
UVM IMPLEMENTS
UVM testbench IMPLEMENTS
uvm-verilator DEPENDS_ON

CITATIONS

11 sources
11 citations
[1] Verilator is an open-source SystemVerilog simulator and lint system, with public repository verilator/verilator. verilator/verilator
[2] Verilator compiles Verilog or SystemVerilog code into an optimized, potentially multithreaded model wrapped in a C++/SystemC module, executing faster than interpreted simulators and on par with or better than many closed-source simulators. Fuzzing IPv4 modules on FPGAs
[3] ProcessorFuzz uses Verilator as the open-source RTL simulator for all evaluated processor designs, comparing RTL trace logs against ISA trace logs. Fuzzing IPv4 modules on FPGAs
[4] RFuzz uses Verilator to simulate the DUT on the CPU side of an SoC, communicating with the fuzzer via shared-memory buffers. Fuzzing IPv4 modules on FPGAs
[5] DirectFuzz builds on RFuzz and likewise uses Verilator for hardware simulation. Fuzzing IPv4 modules on FPGAs
[6] FuSS uses Verilator to convert hardware models into cycle-accurate software models; Verilator serves as the backend due to precise modeling of synthesizable Verilog designs. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[7] The Cascade artifact uses Verilator v5.006 and provides an explicit reinstall procedure if the running Verilator version produces an unknown-warning error. comsec-group/cascade-artifacts
[8] Long-running efforts led by Antmicro, Wilson Snyder, and open-source contributors enable UVM testbenches in Verilator via the uvm-verilator project, with upstream UVM 2017 support as a milestone. CHIPS Alliance SV Tools Project launch
[9] The CHIPS Alliance sv-tests suite tracks Verilator's SystemVerilog feature support and was used to track milestones such as the addition of UVM support to Verilator. CHIPS Alliance SV Tools Project launch
[10] Verilator is discussed in a survey of RISC-V processor verification alongside RVVI-Trace, RVVI-VVP, and RISCV-DV as part of the open-source verification ecosystem. Survey of Verification of RISC-V Processors
[11] A DATE 2022 cross-level processor-verification excerpt references https://www.veripool.org/verilator/ but does not provide enough surrounding detail to support stronger claims about its role in that work. Verilator project page

VERSION HISTORY

v5 · 6/25/2026 · minimax/minimax-m3 (current)
v4 · 5/29/2026 · gpt-5.5
v3 · 5/28/2026 · gpt-5.5
v2 · 5/28/2026 · gpt-5.5
v1 · 5/26/2026 · gpt-5.5