Verilator

Overview

Verilator is an open-source SystemVerilog simulator and lint system. Its public GitHub repository is verilator/verilator. [citation: Verilator is an open-source SystemVerilog simulator and lint system]

Within the provided processor-verification evidence, Verilator is specifically described as an open-source RTL simulator. ProcessorFuzz used Verilator for RTL simulation of all processor designs in its evaluation. [citation: ProcessorFuzz uses Verilator for RTL simulation]

Role in ProcessorFuzz

ProcessorFuzz performs RTL simulation and trace comparison after its transition unit determines that a test input produces a unique CSR transition. For such an input, ProcessorFuzz launches RTL simulation, generates an extended RTL trace log, and compares that RTL trace log with an extended ISA trace log. A difference between the logs is treated as a potential processor-design bug requiring further investigation by a verification engineer. [citation: ProcessorFuzz RTL simulation and trace comparison]

In that workflow, Verilator provides the RTL simulation component. The same evidence states that ProcessorFuzz extends the Spike open-source ISA simulator to store monitored CSR values, while Verilator is used for RTL simulation of the processor designs. [citation: ProcessorFuzz uses Spike for ISA traces and Verilator for RTL simulation]

Relationship to RTL simulation

The evidence supports linking Verilator to RTL simulation: ProcessorFuzz explicitly uses Verilator as an open-source RTL simulator, and the generated RTL trace log is central to ProcessorFuzz's comparison against an ISA trace log. [citation: Verilator as RTL simulator]

Evidence boundaries

A DATE 2022 cross-level processor-verification excerpt includes https://www.veripool.org/verilator/ as a referenced URL, but the excerpt does not provide enough surrounding detail to support a stronger claim about how Verilator was used in that work. [citation: DATE 2022 excerpt references Verilator URL only]